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DS26102 16-Port TDM-to-ATM PHY
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GENERAL DESCRIPTION
On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering (up to 4 cells), HEC generation and insertion, cell scrambling, and converts the data to a serial stream appropriate for interfacing to a T1/E1 framer or transceiver. On the receive side, the DS26102 receives a TDM stream from a T1/E1 framer or transceiver; searches for the cell alignment; verifies the HEC; provides cell filtering, descrambling, and cell buffering; and passes the cells to an ATM device through the UTOPIA II interface. Other low-level traffic management functions are selectable for the transmit and receive paths. The DS26102 can also be used in fractional T1/E1 applications. The DS26102 maps ATM cells to T1/E1 TDM frames as per the ATM Forum Specifications af-phy-0016.000 and af-phy-0064.000. In the receive direction, the cell delineation mechanism used for finding ATM cell boundary within T1/E1 frame is performed as per ITU I.432. The DS26102 provides a mapping solution for up to 16 T1/E1 TDM ports. The terms physical layer (PHY) and line side are used synonymously in this document and refer to the device interfacing with the line side of the DS26102. The terms ATM layer and system side are used synonymously and refer to the DS26102's UTOPIA II interface.
FEATURES
Supports 16 T1/E1 TDM Ports Supports Fractional T1/E1 Compliant to ATM Forum Specifications for ATM Over T1 and E1 Standard UTOPIA II Interface to the ATM Layer Configurable UTOPIA Address Range Configurable Tx FIFO Depth to 2, 3, or 4 Cells Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction per ITU I.432 Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition HEC-Based Cell Delineation Single-Bit HEC Error Correction in the Receive Direction Receive HEC-Errored Cell Filtering Receive Idle/Unassigned Cell Filtering User-Definable Cell Filtering 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor Interface Internal Clock Generator Eliminates External High-Speed Clocks Internal One-Second Timer Detects/Reports Up to Eight External Status Signals with Interrupt Support IEEE 1149.1 JTAG Boundary Scan Support 17mm x 17mm, 256-Pin CSBGA
FUNCTIONAL DIAGRAM
Features continued on page 5.
APPLICATIONS
DSLAMS ATM Over T1/E1 Routers IMA
16 TDM PORTS
DS26102
UTOPIA II
ORDERING INFORMATION
PART DS26102 TEMP RANGE -40C to +85C PIN-PACKAGE 256 CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 021403
DS26102 16-Port TDM-to-ATM PHY
TABLE OF CONTENTS
1. 2. 3. 4. 5. 6. FEATURES ......................................................................................................................................5 APPLICABLE STANDARDS............................................................................................................5 ACRONYMS AND DEFINITIONS.....................................................................................................6 BLOCK DIAGRAM ...........................................................................................................................7 PIN DESCRIPTION ..........................................................................................................................8 SIGNAL DEFINITIONS...................................................................................................................12 6.1 6.2 6.3 TDM SIGNALS ..........................................................................................................................12 UTOPIA-SIDE SIGNALS ............................................................................................................12 MICROPROCESSOR AND SYSTEM INTERFACE SIGNALS ................................................................14
6.4 TEST AND JTAG SIGNALS .........................................................................................................16 7. TRANSMIT OPERATION ...............................................................................................................17 7.1 7.2 7.3 8. UTOPIA-SIDE TRANSMIT--MUXED MODE WITH 1 TXCLAV ........................................................17 UTOPIA-SIDE TRANSMIT--DIRECT STATUS MODE (MULTITXCLAV) .........................................19 TRANSMIT PROCESSING ............................................................................................................20
7.4 PHYSICAL-SIDE TRANSMIT.........................................................................................................21 RECEIVE OPERATION..................................................................................................................23 8.1 8.2 8.3 PHYSICAL-SIDE RECEIVE...........................................................................................................23 RECEIVE PROCESSING ..............................................................................................................25 UTOPIA-SIDE RECEIVE--MUXED MODE WITH 1 RXCLAV..........................................................27
8.4 UTOPIA-SIDE RECEIVE--DIRECT STATUS MODE (MULTIRXCLAV) ...........................................28 9. REGISTER MAPPING....................................................................................................................30 10. REGISTER DEFINITIONS..............................................................................................................31 10.1 10.2 TRANSMIT REGISTERS ..............................................................................................................31 STATUS REGISTERS..................................................................................................................35
10.3 RECEIVE REGISTERS ................................................................................................................36 11. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT....................................45 11.1 INSTRUCTION REGISTER............................................................................................................48 11.2 TEST REGISTERS......................................................................................................................49 12. OPERATING PARAMETERS.........................................................................................................52 13. CRITICAL TIMING INFORMATION................................................................................................53 14. THERMAL INFORMATION ............................................................................................................59 15. APPLICATIONS INFORMATION ...................................................................................................60 15.1 15.2 APPLICATION IN ATM USER-NETWORK INTERFACES ...................................................................60 INTERFACING WITH FRAMERS ....................................................................................................60
15.3 FRACTIONAL T1/E1 SUPPORT ...................................................................................................61 16. PACKAGE INFORMATION............................................................................................................62 17. REVISION HISTORY......................................................................................................................64
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TABLE OF FIGURES
Figure 4-1. Block Diagram ....................................................................................................................... 7 Figure 7-1. Polling Phase and Selection Phase at Transmit Interface.....................................................18 Figure 7-2. End and Restart of Cell at Transmit Interface .......................................................................18 Figure 7-3. Transmission to PHY Paused for Three Cycles ....................................................................19 Figure 7-4. Example of Direct Status Indication, Transmit Direction .......................................................20 Figure 7-5. Transmit Cell Flow and Processing ......................................................................................21 Figure 7-6. Transmit Framer Interface in TFP Mode for T1.....................................................................22 Figure 7-7. Transmit Framer Interface in Gapped-Clock Mode for T1.....................................................22 Figure 7-8. Transmit Framer Interface in TFP Mode for E1.....................................................................22 Figure 7-9. Transmit Framer Interface in Gapped-Clock Mode for E1.....................................................23 Figure 8-1. Receive Framer Interface in RFP Mode for T1 .....................................................................24 Figure 8-2. Receive Framer Interface in Gapped-Clock Mode for T1......................................................24 Figure 8-3. Receive Framer Interface in RFP Mode for E1 .....................................................................25 Figure 8-4. Receive Framer Interface in Gapped-Clock Mode for E1......................................................25 Figure 8-5. Cell Delineation State Diagram.............................................................................................26 Figure 8-6. Header Correction State Machine.........................................................................................26 Figure 8-7. Polling Phase and Selection at Receive Interface.................................................................27 Figure 8-8. End and Restart of Cell Transmission at Receive Interface ..................................................28 Figure 8-9. Example Direct Status Indication, Receive Direction ............................................................29 Figure 10-1. Accessing Tx PMON Counter.............................................................................................34 Figure 10-2. Accessing Rx PMON Counters...........................................................................................40 Figure 11-1. JTAG Functional Block Diagram.........................................................................................45 Figure 11-2. TAP Controller State Diagram ............................................................................................47 Figure 13-1. Intel Bus Read Timing (BTS = 0/MUX = 1) .........................................................................53 Figure 13-2. Intel Bus Write Timing (BTS = 0/MUX = 1) .........................................................................54 Figure 13-3. Motorola Bus Timing (BTS = 1/MUX = 1)............................................................................54 Figure 13-4. Intel Bus Read Timing (BTS = 0/MUX = 0) .........................................................................55 Figure 13-5. Intel Bus Write Timing (BTS = 0/MUX = 0) .........................................................................56 Figure 13-6. Motorola Bus Read Timing (BTS = 1/MUX = 0) ..................................................................56 Figure 13-7. Motorola Bus Write Timing (BTS = 1/MUX = 0) ..................................................................56 Figure 13-8. Setup/Hold Time Definition .................................................................................................58 Figure 13-9. Delay Time Definition .........................................................................................................58 Figure 13-10. JTAG Interface Timing Diagram .......................................................................................58 Figure 15-1. User-Network Interface Application ....................................................................................60 Figure 15-2. DS26102 Interfacing with Dallas Framer in Framing-Pulse Mode .......................................61
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DS26102 16-Port TDM-to-ATM PHY
LIST OF TABLES
Table 5-A. Pin Description List ................................................................................................................ 8 Table 9-A. Register Map.........................................................................................................................30 Table 11-A. Instruction Codes for IEEE 1149.1 Architecture...................................................................48 Table 11-B. ID Code Structure ...............................................................................................................48 Table 11-C. Device ID Codes .................................................................................................................48 Table 11-D. Boundary Scan Control Bits ................................................................................................49 Table 13-A. AC Characteristics--Multiplexed Parallel Port (MUX = 1)....................................................53 Table 13-B. AC Characteristics--Nonmultiplexed Parallel Port (MUX = 1) .............................................55 Table 13-C. Framer Interface AC Characteristics ...................................................................................57 Table 13-D. UTOPIA Transmit AC Characteristics .................................................................................57 Table 13-E. UTOPIA Receive AC Characteristics...................................................................................57 Table 13-F. JTAG Interface Timing.........................................................................................................58 Table 13-G. System Clock AC Characteristics........................................................................................59 Table 14-A. Thermal Properties, Natural Convection..............................................................................59 Table 14-B. Theta-JA (qJA) vs. Airflow.....................................................................................................59 Table 15-A. Suggested Clock Edge Configurations ................................................................................61 Table 15-B. Fractional T1/E1 Register Settings ......................................................................................61
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DS26102 16-Port TDM-to-ATM PHY
1. FEATURES

Supports 16 T1/E1 Ports Supports Fractional T1/E1 and Arbitrary Bit Rates in Multiples of 64kbps (DS0/TS) Up to 2.048Mbps Supports Clear E1 Compliant to the ATM Forum Specifications for ATM Over T1 and E1 Standard UTOPIA II Interface to the ATM Layer Configurable UTOPIA Address Range Generic 8-Bit Asynchronous Microprocessor Interface for Configuration and Status Indications Including Interrupt Capability Physical Layer Interface Can Accept T1/E1 TDM Stream in the Form of Either (1) Clock, Data, and Frame-Overhead Indication or (2) Gapped Clock (Gapped at Overhead Positions in the Frame) and Data Selectable Active Clock Edge for Interface with the T1/E1 Framer Supports Diagnostic Loopback Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction as per the ITU I.432 for the Cell-Based Physical Layer Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition Option of Using Either Idle or Unassigned Cells for Cell-Rate Decoupling in Transmit Direction

1-Byte Programmable Pattern for Payload of Cells Used for Cell-Rate Decoupling Tx FIFO Depth Configurable to Either 2, 3, or 4 Cells Transmit FIFO Depth Indication for 2-Cell Space Through External Pins Optional Single-Bit HEC Error Insertion HEC-Based Cell Delineation as per I.432 Optional Single-Bit HEC Error Correction in the Receive Direction Optional Filtering of HEC-Errored Cells Received Optional Receive Idle/Unassigned Cell Filtering Optional User-Defined Cell Filtering Based on Programmable Header Bits Programmable Loss-Of-Cell Delineation (LCD) Integration and Interrupt Interrupt for FIFO Overrun in Receive Direction Saturating Counts for (1) Number of Error-Free Assigned Cells Received and Transmitted and (2) Number of Correctable and Uncorrectable HEC-Errored Cells Received Selectable Internally Generated Clock (System Clock Divided by 8) in Diagnostic Loopback Mode Integrated PLL Generates High-Frequency Clocks IEEE 1149.1 JTAG Boundary Scan Support
2. APPLICABLE STANDARDS
[1] ATM Forum "DS1 Physical Layer Specification," af-phy-0016.000, September 1994 [2] ATM Forum "E1 Physical Layer Specification," af-phy-0064.000, September 1996 [3] ATM Forum "UTOPIA Level 2 Specification," Version 1.0, af-phy-0039.000, June 1995 [4] B-ISDN User-Network Interface--Physical Layer Specification--ITU-T Recommendation I.432--3/93
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DS26102 16-Port TDM-to-ATM PHY
3. ACRONYMS AND DEFINITIONS
ACRONYM ATM CRC DPRAM FIFO HEC IMA P s LCD ms OAM OCD PMON Rx DS0 TS Tx UTOPIA DESCRIPTION Asynchronous Transfer Mode Cyclic Redundancy Check Dual Port Random Access Memory First In, First Out (Memory) Header Error Check Inverse Multiplexing for ATM Microprocessor Microsecond Loss-of-Cell Delineation Millisecond Operations Administration and Maintenance Out-of-Loss Delineation Performance Monitoring Receive Each 64kbps Channel in DS1 Frame Each 64kbps Channel in E1 Frame (Time Slot) Transmit Universal Test and Operations PHY Interface for ATM
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DS26102 16-Port TDM-to-ATM PHY
4. BLOCK DIAGRAM
Figure 4-1. Block Diagram
DS26102
RCLK0-15
16
16
RLCD0-15 UR-ENB UR-SOC UR-CLK
RDATA0-15
16
RECEIVE TDM INTERFACE
CONTROL SCRAMBLING AND RATE DECOUPLING
CELL STORAGE FIFO
RECEIVE UTOPIA BUS INTERFACE
4 5 8
UR-CLAV0-3
UR-ADDR0-4 UR-DATA0-7 UR-PAR REFCLKIN GCLKOUT GCLKIN TEST UT-ENB UT-SOC UT-CLK
RFP0-15
16
CLOCK PLL
TCLK0-15
16
TDATA0-15
16
TRANSMIT TDM INTERFACE
CONTROL SCRAMBLING AND RATE DECOUPLING
CELL STORAGE FIFO
TRANSMIT UTOPIA BUS INTERFACE
4 4 5 8
UT-CLAV0 -3 UT-2CLAV0 -3
UT_PAR UT-ADDR0-4 UT-DATA0-7 8KHZIN 1SECOUT
TFP0-15
16
1-SECOND TIMER
CONTROLLER INTERFACE
8 7 8
JTAG
CS
RD (DS)
INT
A7/ALE (AS)
WR (R/W)
BLS0 EXSTAT0-7
BTS
MUX
A0-A6
RESET
AD0-AD7
JTRST JTDI JTDO JTCLK
JTMS
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5. PIN DESCRIPTION
Table 5-A. Pin Description List
PIN J13 J12 F16 F13 F12 G15 G14 G16 G13 G12 C14 C16 D14 D16 E15 E14 E16 E13 E12 F15 F14 J16 J14 J15 H12 H13 H16 H14 H15 K13 K12 B16 P16 N16 N15 P15 N14 C15 A1, A15, A16, B1, B2, B15, C1, C2, L16, P3, R1, R2, R15, R16, T1, T2, T16 A14 B13 N8 P7 R8 T9 M10 P10 C12 D11 B11 A10 E9 C9 NAME 1SECOUT 8KHZIN A0 A1 A2 A3 A4 A5 A6 A7/ALE (AS) BLS0 BTS CS D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 EXSTAT0 EXSTAT1 EXSTAT2 EXSTAT3 EXSTAT4 EXSTAT5 EXSTAT6 EXSTAT7 GCLKIN GCLKOUT INT JTCLK JTDI JTDO JTMS JTRST MUX N.C. RCLK0 RCLK1 RCLK11 RCLK10 RCLK12 RCLK13 RCLK14 RCLK15 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 I/O O I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I O O I I O I I I -- I I I I I I I I I I I I I I FUNCTION One-Second Reference 8kHz Clock for One-Second Timer P Address Bus Bit 0 P Address Bus Bit 1 P Address Bus Bit 2 P Address Bus Bit 3 P Address Bus Bit 4 P Address Bus Bit 5 P Address Bus Bit 6 P Address Bus Bit 7 (Note 1) Block Select 0 Bus Type Select (0 = Intel) Chip Select (Active Low) P Data 0/Address/Data 0 P Data 1/Address/Data 1 P Data 2/Address/Data 2 P Data 3/Address/Data 3 P Data 4/Address/Data 4 P Data 5/Address/Data 5 P Data 6/Address/Data 6 P Data 7/Address/Data 7 External Status Input External Status Input External Status Input External Status Input External Status Input External Status Input External Status Input External Status Input High-Frequency Clock Input High-Frequency Clock Output Interrupt Signal (Active Low) (Note 2) IEEE 1149.1 Test Clock IEEE 1149.1 Test Data Input IEEE 1149.1 Test Data Output IEEE 1149.1 Test Mode Select IEEE 1149.1 Reset Bus Mode Select (0 = Nonmuxed) No Connect Rx Line Clock for Port 0 Rx Line Clock for Port 1 Rx Line Clock for Port 11 Rx Line Clock for Port 10 Rx Line Clock for Port 12 Rx Line Clock for Port 13 Rx Line Clock for Port 14 Rx Line Clock for Port 15 Rx Line Clock for Port 2 Rx Line Clock for Port 3 Rx Line Clock for Port 4 Rx Line Clock for Port 5 Rx Line Clock for Port 6 Rx Line Clock for Port 7
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DS26102 16-Port TDM-to-ATM PHY
PIN T6 M7 D15 B14 A13 T7 M8 P8 N9 R9 T10 A12 E11 C11 D10 B10 A9 N6 R6 L15 L14 C13 D12 R7 T8 M9 P9 N10 R10 B12 A11 E10 C10 D9 B9 P6 N7 N1 N2 R4 N5 T5 P5 R5 M6 N4 N3 P1 P2 R3 T3 P4 T4 J3 J1 J4 J5 H2 NAME RCLK8 RCLK9 RD (DS) RDATA0 RDATA1 RDATA10 RDATA11 RDATA12 RDATA13 RDATA14 RDATA15 RDATA2 RDATA3 RDATA4 RDATA5 RDATA6 RDATA7 RDATA8 RDATA9 REFCLKIN RESET RFP0 RFP1 RFP10 RFP11 RFP12 RFP13 RFP14 RFP15 RFP2 RFP3 RFP4 RFP5 RFP6 RFP7 RFP8 RFP9 RLCD0 RLCD1 RLCD10 RLCD11 RLCD12 RLCD13 RLCD14 RLCD15 RLCD2 RLCD3 RLCD4 RLCD5 RLCD6 RLCD7 RLCD8 RLCD9 UR_ADDR0 UR_ADDR1 UR_ADDR2 UR_ADDR3 UR_ADDR4 I/O I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O I I I I I FUNCTION Rx Line Clock for Port 8 Rx Line Clock for Port 9 Read Enable (Active Low) Rx Line Serial Data for Port 0 Rx Line Serial Data for Port 1 Rx Line Serial Data for Port 10 Rx Line Serial Data for Port 11 Rx Line Serial Data for Port 12 Rx Line Serial Data for Port 13 Rx Line Serial Data for Port 14 Rx Line Serial Data for Port 15 Rx Line Serial Data for Port 2 Rx Line Serial Data for Port 3 Rx Line Serial Data for Port 4 Rx Line Serial Data for Port 5 Rx Line Serial Data for Port 6 Rx Line Serial Data for Port 7 Rx Line Serial Data for Port 8 Rx Line Serial Data for Port 9 1.544MHz/2.048MHz Reference Clock Device Reset (Active Low) Rx Frame Pulse for Port 0 Rx Frame Pulse for Port 1 Rx Frame Pulse for Port 10 Rx Frame Pulse for Port 11 Rx Frame Pulse for Port 12 Rx Frame Pulse for Port 13 Rx Frame Pulse for Port 14 Rx Frame Pulse for Port 15 Rx Frame Pulse for Port 2 Rx Frame Pulse for Port 3 Rx Frame Pulse for Port 4 Rx Frame Pulse for Port 5 Rx Frame Pulse for Port 6 Rx Frame Pulse for Port 7 Rx Frame Pulse for Port 8 Rx Frame Pulse for Port 9 Rx Loss-of-Cell Delineation Port 0 Rx Loss-of-Cell Delineation Port 1 Rx Loss-of-Cell Delineation Port 10 Rx Loss-of-Cell Delineation Port 11 Rx Loss-of-Cell Delineation Port 12 Rx Loss-of-Cell Delineation Port 13 Rx Loss-of-Cell Delineation Port 14 Rx Loss-of-Cell Delineation Port 15 Rx Loss-of-Cell Delineation Port 2 Rx Loss-of-Cell Delineation Port 3 Rx Loss-of-Cell Delineation Port 4 Rx Loss-of-Cell Delineation Port 5 Rx Loss-of-Cell Delineation Port 6 Rx Loss-of-Cell Delineation Port 7 Rx Loss-of-Cell Delineation Port 8 Rx Loss-of-Cell Delineation Port 9 Rx UTOPIA Address 0 (LSB) Rx UTOPIA Address 1 Rx UTOPIA Address 2 Rx UTOPIA Address 3 Rx UTOPIA Address 4 (MSB)
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PIN M5 M4 M1 M3 K5 L3 L1 L4 L5 K2 K3 K1 K4 J2 M2 L2 D8 B8 T12 T13 P13 P14 M16 L12 A7 E6 C6 D5 B5 D4 N11 R11 E8 C8 N12 R12 N13 R14 M13 M15 D7 B7 A6 E5 C5 B4 M11 P11 K16 A8 E7 P12 R13 T14 T15 M14 L13 C7 NAME UR_CLAV0 UR_CLAV1 UR_CLAV2 UR_CLAV3 UR_CLK UR_DATA0 UR_DATA1 UR_DATA2 UR_DATA3 UR_DATA4 UR_DATA5 UR_DATA6 UR_DATA7 UR_ENB UR_PAR UR_SOC TCLK0 TCLK1 TCLK10 TCLK11 TCLK12 TCLK13 TCLK14 TCLK15 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 TCLK9 TDATA0 TDATA1 TDATA10 TDATA11 TDATA12 TDATA13 TDATA14 TDATA15 TDATA2 TDATA3 TDATA4 TDATA5 TDATA6 TDATA7 TDATA8 TDATA9 TEST TFP0 TFP1 TFP10 TFP11 TFP12 TFP13 TFP14 TFP15 TFP2 I/O O O O O I O O O O O O O O I O O I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O FUNCTION Rx UTOPIA Cell Available 0 Rx UTOPIA Cell Available 1 Rx UTOPIA Cell Available 2 Rx UTOPIA Cell Available 3 Rx UTOPIA Clock Rx UTOPIA Data Bus 0 (LSB) Rx UTOPIA Data Bus 1 Rx UTOPIA Data Bus 2 Rx UTOPIA Data Bus 3 Rx UTOPIA Data Bus 4 Rx UTOPIA Data Bus 5 Rx UTOPIA Data Bus 6 Rx UTOPIA Data Bus 7 (MSB) Rx UTOPIA Enable (Active Low) Rx UTOPIA Parity Bit Rx UTOPIA Start of Cell Tx Line Clock for Port 0 Tx Line Clock for Port 1 Tx Line Clock for Port 10 Tx Line Clock for Port 11 Tx Line Clock for Port 12 Tx Line Clock for Port 13 Tx Line Clock for Port 14 Tx Line Clock for Port 15 Tx Line Clock for Port 2 Tx Line Clock for Port 3 Tx Line Clock for Port 4 Tx Line Clock for Port 5 Tx Line Clock for Port 6 Tx Line Clock for Port 7 Tx Line Clock for Port 8 Tx Line Clock for Port 9 Tx Line Serial Data for Port 0 Tx Line Serial Data for Port 1 Tx Line Serial Data for Port 10 Tx Line Serial Data for Port 11 Tx Line Serial Data for Port 12 Tx Line Serial Data for Port 13 Tx Line Serial Data for Port 14 Tx Line Serial Data for Port 15 Tx Line Serial Data for Port 2 Tx Line Serial Data for Port 3 Tx Line Serial Data for Port 4 Tx Line Serial Data for Port 5 Tx Line Serial Data for Port 6 Tx Line Serial Data for Port 7 Tx Line Serial Data for Port 8 Tx Line Serial Data for Port 9 Test Control Tx Frame Pulse for Port 0 Tx Frame Pulse for Port 1 Tx Frame Pulse for Port 10 Tx Frame Pulse for Port 11 Tx Frame Pulse for Port 12 Tx Frame Pulse for Port 13 Tx Frame Pulse for Port 14 Tx Frame Pulse for Port 15 Tx Frame Pulse for Port 2
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PIN D6 B6 A5 A4 C4 T11 M12 G1 H4 H1 H3 D3 A2 C3 B3 A3 G4 G3 G2 H5 F2 F1 F4 F5 E2 E3 E1 E4 D2 D1 G5 F3 F8, F9, G8, G9, H6, H7, H10, H11, J6, J7, J10, J11, K8, K9, L8, L9 F6, F7, F10, F11, G6, G7, G10, G11, H8, H9, J8, J9, K6, K7, K10, K11, K14, K15, L6, L7, L10, L11 D13 NAME TFP3 TFP4 TFP5 TFP6 TFP7 TFP8 TFP9 UT_2CLAV0 UT_2CLAV1 UT_2CLAV2 UT_2CLAV3 UT_ADDR0 UT_ADDR1 UT_ADDR2 UT_ADDR3 UT_ADDR4 UT_CLAV0 UT_CLAV1 UT_CLAV2 UT_CLAV3 UT_CLK UT_DATA0 UT_DATA1 UT_DATA2 UT_DATA3 UT_DATA4 UT_DATA5 UT_DATA6 UT_DATA7 UT_ENB UT_PAR UT_SOC VDD I/O I/O I/O I/O I/O I/O I/O I/O O O O O I I I I I O O O O I I I I I I I I I I I I -- FUNCTION Tx Frame Pulse for Port 3 Tx Frame Pulse for Port 4 Tx Frame Pulse for Port 5 Tx Frame Pulse for Port 6 Tx Frame Pulse for Port 7 Tx Frame Pulse for Port 8 Tx Frame Pulse for Port 9 Tx UTOPIA 2 Cells Available 0 Tx UTOPIA 2 Cells Available 1 Tx UTOPIA 2 Cells Available 2 Tx UTOPIA 2 Cells Available 3 Tx UTOPIA Address 0 (LSB) Tx UTOPIA Address 1 Tx UTOPIA Address 2 Tx UTOPIA Address 3 Tx UTOPIA Address 4 (MSB) Tx UTOPIA Cell Available 0 Tx UTOPIA Cell Available 1 Tx UTOPIA Cell Available 2 Tx UTOPIA Cell Available 3 Tx UTOPIA Clock Tx UTOPIA Data Bus 0 (LSB) Tx UTOPIA Data Bus 1 Tx UTOPIA Data Bus 2 Tx UTOPIA Data Bus 3 Tx UTOPIA Data Bus 4 Tx UTOPIA Data Bus 5 Tx UTOPIA Data Bus 6 Tx UTOPIA Data Bus 7 (MSB) Tx UTOPIA Enable (Active Low) Tx UTOPIA Parity Bit Tx UTOPIA Start of Cell Positive Supply
VSS WR (R/W)
-- I
Ground Write Enable (Active Low)
Note 1: Address-latch enable for muxed bus. Note 2: Open-drain output.
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6. SIGNAL DEFINITIONS
6.1 TDM Signals
RCLK0-15 Signal Name: Receive Line Clock (Ports 0 to 15) Signal Description: Input Signal Type: The physical layer device uses the RCLK input to latch the RDATA and RFP signals. RDATA and RFP are sampled by the receive section of the DS26102 at either the positive edge or negative edge of RCLK, as controlled by the RAES (RCR2.2) control bit. RCLK is gapped during nonactive and framing bit positions in gapped-clock mode (RPLIM = 1). RCLK should be glitch-free. RDATA0-15 Signal Name: Receive Line Data (Ports 0 to 15) Signal Description: Input Signal Type: The RDATA input carries the receive bit stream. If the RCLK is gapped at framing bit positions, RDATA is then sampled at every RCLK tick. If RCLK is not gapped and RFP is used to indicate framing bit positions, the RDATA bits that are not associated with framing-overhead bits are sampled and cell delineated. In clear E1, RDATA is sampled at every RCLK tick. RFP0-15 Signal Name: Receive Frame Pulse (Ports 0 to 15) Signal Description: Input Signal Type: This active-high signal indicates the framing-overhead bit positions corresponding to RDATA. For T1/E1, this aligns with the first bit of the T1/E1 frame. For T1, RDATA coming at the RFP position is ignored. For E1, RFP is used to identify TS0 (RFP position is bit 0 of TS0) and TS16 locations, and RDATA coming at these slots are ignored. In clear E1, RFP is ignored. In frame-pulse mode, the RFP should come once every 125ms. TCLK0-15 Signal Name: Transmit Line Clock (Ports 0 to 15) Signal Description: Input Signal Type: The TCLK input is used by the DS26102's transmit section to launch TDATA and TFP (when configured as an output) at either positive edge or negative edge, as controlled by the TAES (TCR2.2) control bit. TDATA0-15 Signal Name: Transmit Line Data (Ports 0 to 15) Signal Description: Output Signal Type: The TDATA output carries the transmit bit stream. ATM layer data bits are not transmitted during framing/overhead bit locations. TDATA is output at the TCLK configured active edge. TFP0-15 Signal Name: Transmit Frame Pulse (Ports 0 to 15) Signal Description: Input/Output Signal Type: This active-high signal can be set as an input or an output by using the TFSD (TCR2.0) control bit. TFP indicates the frame-overhead bit positions corresponding to TDATA. For T1/E1, this signal aligns with the first bit of the T1/E1 frame. For T1, TDATA coming at the TFP position does not contain valid data bit. For E1, TFP is used to identify TS0 (TFP position is bit 0 of TS0) and TS16. TDATA does not contain valid data at these locations. After RESET, the DS26102 is configured to use this signal as an input. In frame-pulse mode, the TFP should occur once every 125ms.
6.2
UTOPIA-Side Signals
UR_CLK Signal Name: Receive UTOPIA Clock Signal Description: Input Signal Type: This clock is used to register and control all other UTOPIA signals on the receive side.
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DS26102 16-Port TDM-to-ATM PHY UR_ADDR[4:0] Signal Name: Receive UTOPIA Address Signal Description: Input Signal Type: The ATM layer drives this 5-bit UTOPIA address bus to select the appropriate UTOPIA port. UR_ADDR4 is the MSB and UR_ADDR0 is the LSB. Signal Name: UR_ENB Receive UTOPIA Enable Signal Description: Input Signal Type: The ATM layer asserts this active-low signal to indicate that UR_DATA and UR_SOC are sampled at the end of the next cycle. UR_SOC Signal Name: Receive UTOPIA Start of Cell Signal Description: Output Signal Type: The DS26102 asserts this active-high, tri-statable signal when UR_DATA contains the first valid byte of a cell. UR_SOC is enabled only in cycles following those with UR_ENB asserted while a cell transfer is in progress. UR_DATA[7:0] Signal Name: Receive UTOPIA Data Bus Signal Description: Output Signal Type: The DS26102 drives this byte-wide data bus in response to the selection of one of the UTOPIA ports by the ATM layer for cell transfer. This bus is three-statable, and is enabled only in cycles following those that have UR_ENB asserted and a cell transfer in progress for a port. UR_DATA7 is the MSB and UR_DATA0 is the LSB. UR_CLAV[3:0] Signal Name: Receive UTOPIA Cell Available Signal Description: Output Signal Type: The active-high UR_CLAV signals are asserted if a complete cell is available for transfer to the ATM layer for the polled port. If UR_ADDR does not match any of the UTOPIA port addresses, this signal is tri-stated. UR_CLAV0 is driven in multiplexed with 1 CLAV polling mode as well as direct status mode for port 1. UR_CLAV3, UR_CLAV2, and UR_CLAV1 are driven only in direct status mode for ports 4, 3, and 2, respectively. UR_PAR Signal Name: Receive UTOPIA Parity Bit Signal Description: Output Signal Type: This three-statable signal allows for parity error checking, as calculated for the 8-bits of the UR_DATA bus, and can represent odd or even parity as determined by the receive parity select bit (RPS) in RCR1. UT_CLK Signal Name: Transmit UTOPIA Clock Signal Description: Input Signal Type: This clock is used to register and control the UTOPIA signals on the transmit side. UT_ADDR[4:0] Signal Name: Transmit UTOPIA Address Signal Description: Input Signal Type: The ATM layer drives this 5-bit-wide bus to poll and select the appropriate UTOPIA port. UT_ADDR4 is the MSB and UT_ADDR0 is the LSB. Signal Name: UT_ENB Transmit UTOPIA Enable Signal Description: Input Signal Type: The ATM layer asserts this active-low enable signal during cycles when UT_DATA contains valid cell data.
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DS26102 16-Port TDM-to-ATM PHY UT_SOC Signal Name: Transmit UTOPIA Start of Cell Signal Description: Input Signal Type: The ATM layer asserts this active-high signal when UT_DATA contains the first valid byte of the cell. UT_DATA[7:0] Signal Name: Transmit UTOPIA Data Bus Signal Description: Input Signal Type: The ATM layer drives this byte-wide true data to one of the selected ports. UT_DATA7 is the MSB and UT_DATA0 is the LSB. UT_CLAV[3:0] Signal Name: Transmit UTOPIA Cell Available Signal Description: Output Signal Type: The DS26102 asserts this active-high UT_CLAV signal if it has cell space available to accommodate a complete cell from the ATM layer to the polled port. If UT_ADDR does not match with any one of the UTOPIA port addresses, this signal is tri-stated. UT_CLAV0 is driven in multiplexed with 1 CLAV polling mode as well as direct status mode for port 1. UT_CLAV3, UT_CLAV2, and UT_CLAV1 are driven only in direct status mode for ports 4, 3, and 2, respectively. UT_2CLAV[3:0] Signal Name: Transmit UTOPIA 2 Cells Available Signal Description: Output Signal Type: The DS26102 asserts this active-high UT_2CLAV signal if it has cell space available to accommodate two complete cells from the ATM layer. If UT_ADDR does not match with any one of the UTOPIA port addresses, this signal is tri-stated. UT_2CLAV0 is driven in multiplexed with 2 CLAV polling mode as well as direct status mode for port 1. UT_2CLAV3, UT_2CLAV2, and UT_2CLAV1 are driven only in direct status mode for ports 4, 3, and 2, respectively. UT_PAR Signal Name: Transmit UTOPIA Parity Bit Signal Description: Input Signal Type: This signal is used for parity checking as calculated for the 8 bits of the UT_DATA bus. Transmit parity errors are reported in the port status register (PSR) at bit 6. This bit can represent odd or even parity, as determined by the transmit parity select (TPRS) bit in TCR1.
6.3
Microprocessor and System Interface Signals
A[6:0] Signal Name: Microprocessor Address Bus Signal Description: Input Signal Type: This bus selects a specific register in the DS26102 during read/write access. A7 is the MSB and A0 is the LSB. A7 is also used as the address latch enable (ALE/AS) during multiplexed bus operation (MUX = 1). A7/ALE (AS) Signal Name: Address Latch Enable (Address Strobe) or A7 Signal Description: Input Signal Type: In nonmultiplexed bus operation (MUX = 0), the ALE serves as the upper address bit. In multiplexed bus operation (MUX = 1), it serves to demultiplex the bus on a positive-going edge. D[7:0]/AD[7:0] Signal Name: Microprocessor Data Bus Signal Description: Input/Output Signal Type: This 8-bit, bidirectional data bus is used for read/write access of the DS26102's information and control registers. D7/AD7 is the MSB and D0/AD0 is the LSB. This bus also carries address information during multiplexed operation (MUX = 1).
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DS26102 16-Port TDM-to-ATM PHY Signal Name: CS Chip Select Signal Description: Input Signal Type: This active-low signal is used to qualify register read/write accesses. The RD and WR signals are qualified with CS. Signal Name: RD (DS) Read Enable Signal Description: Input Signal Type: Along with CS, this active-low signal qualifies read access to one of the DS26102 registers. While RD and CS are both low, the DS26102 drives the D/AD bus with the contents of the addressed register. Signal Name: WR (R/W) Write Enable Signal Description: Input Signal Type: Along with CS, this active-low signal qualifies write access to one of the DS26102 registers. Data at D/AD[7:0] is written into the addressed register at the rising edge of WR while CS is low. Signal Name: INT Interrupt Signal Description: Output Signal Type: This active-low, open-drain output is asserted when an unmasked interrupt event is detected. INT is deasserted when all interrupts have been acknowledged and serviced. MUX Signal Name: Bus Operation Signal Description: Input Signal Type: Set this signal low to select nonmultiplexed bus operation. Set it high to select multiplexed bus operation. BTS Signal Name: Bus Type Select Signal Description: Input Signal Type: Set this signal high to select Motorola bus timing; set it low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS), and WR (R/W) pins. If BTS = 1, these pins assume the function listed in parentheses (). BLS0 Signal Name: Block Select 0 Signal Description: Input Signal Type: This signal is available on the DS26102 to determine which octal block of ports is mapped to the microprocessor control port. REFCLKIN Signal Name: Reference Clock Signal Description: Input Signal Type: This continuous T1 (1.544MHz) or E1 (2.048MHz) clock is used to create GCLKOUT. GCLKOUT Signal Name: Global Clock Output Signal Description: Output Signal Type: This output clock is 16x the REFCLKIN input (24.7MHz (typ) for T1). This pin is usually connected to GCLKIN. GCLKIN Signal Name: Global Clock Input Signal Description: Input Signal Type: This is the primary clock for internal state machines. It can be connected to GCLKOUT or provided by the user. The GCLKIN frequency must be at least 10x the T1 or E1 line rate.
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DS26102 16-Port TDM-to-ATM PHY RESET Signal Name: System Reset Signal Description: Input Signal Type: This is an active-low reset. Forcing this input low sets all internal registers to their default value. 8KHZIN Signal Name: 8kHz Reference Clock Signal Description: Input Signal Type: This continuous clock is used to generate the internal one-second-timer pulse. It can be a T1/E1 frame sync. 1SECOUT Signal Name: One-Second Clock Output Signal Description: Output Signal Type: This is a one-second reference-pulse output created by dividing 8KHzIN by 8000. Using this signal is optional. EXSTAT0-8 Signal Name: External Status Input (1 to 8) Signal Description: Input Signal Type: A low-to-high transition on this pin sets the EXSTAT status bit in the port status register (PSR). EXSTAT1 maps to the PSR for port 1 up to EXSTAT8, which maps to port 8. The EXSTAT bit can be enabled to generate an interrupt by setting the EXSTATIM bit in RCR2. These signals could be connected to an external event timer, an external status signal, or the 1SECOUT signal generated by the DS26102. Application of this signal is optional. If not used, the EXSTAT signals should be grounded. RLCD0-15 Signal Name: Receive Loss-of-Cell Delineation for Ports 1 to 15 Signal Description: Output Signal Type: This signal is the hardware representation of the LCDS status bit (PSR.2). For example, if RLCD3 is high (logic 1), then port 3's receiver has lost cell delineation (synchronization) with the incoming data stream.
6.4
Test and JTAG Signals
JTRST Signal Name: IEEE 1149.1 Test Reset Signal Description: Input Signal Type: JTRST is used to asynchronously reset the test access port (TAP) controller. After power-up, JTRST must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled high internally through a 10k resistor operation. If boundary scan is not used, this pin should be held low. JTMS Signal Name: IEEE 1149.1 Test Mode Select Signal Description: Input Signal Type: This pin is sampled on the rising edge of JTCLK and is used to place the TAP into the various defined IEEE 1149.1 states. This pin has a 10k pullup resistor. JTCLK Signal Name: IEEE 1149.1 Test Clock Signal Signal Description: Input Signal Type: This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. JTDI Signal Name: IEEE 1149.1 Test Data Input Signal Description: Input Signal Type: Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor.
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DS26102 16-Port TDM-to-ATM PHY JTDO Signal Name: IEEE 1149.1 Test Data Output Signal Description: Output Signal Type: Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected. TEST Signal Name: Test Mode Signal Description: Input Signal Type: When TEST is set to logic 1, the REFCLKIN input is connected to the internal SYS_CLK for the IP01 logic cores. In this mode, the signal on REFCLKIN should be phase-aligned to GCLKIN with a frequency of GCLK/2. Also, when TEST = 1 and RESET = 0, all outputs of the DS26102 should be tri-stated.
7. TRANSMIT OPERATION
The DS26102 interface to the ATM layer is fully compliant to the ATM Forum's UTOPIA Level 2 specification. The DS26102 supports multiplexed with 1 CLAV handshaking only. Each octal block can be configured to use any of the address ranges (0 to 7, 8 to 15, 16 to 23, or 24 to 30) as UTOPIA port addresses. Each octal block on the bus must be configured for a different UTOPIA address range. The depth of the Tx FIFO is configurable to 2, 3, or 4 cells. When a port is polled and has cell space available, the DS26102 generates a cell-available signal for that port. Figure 7-1 shows the polling and cell transfer cycles to UTOPIA ports in the DS26102. Note that UT_SOC must be aligned with the first byte transfer. The DS26102 uses UT_SOC to detect the first byte of a cell. If a spurious UT_SOC comes during a cell transfer, then the DS26102 aligns with the latest UT_SOC and ignores the bytes (partial cell) received thus far.
7.1
UTOPIA-Side Transmit--Muxed Mode with 1 TXCLAV
In Level 1 UTOPIA there is only one PHY layer device. It uses UT_CLAV to convey transfer status to the ATM layer. In Level 2 UTOPIA only one MPHY port at a time is selected for a cell transfer. However, another MPHY port can be polled for its UT_CLAV status, while the selected MPHY port (device) transfers data. The ATM layer polls the UT_CLAV status of an MPHY port by placing its address on UT_ADDR. The MPHY port (device) drives UT_CLAV during each cycle, following one with its address on the UT_ADDR lines. The ATM layer selects an MPHY port for transfer by placing the desired MPHY port address onto UT_ADDR, when UT_ENB is deasserted during the current clock cycle and asserted during the next clock cycle. All MPHY devices only examine the value on UT_ADDR for selection purposes when UT_ENB is deasserted. The MPHY port is selected starting from the cycle after its address is on the UT_ADDR lines and UT_ENB is deasserted; a new MPHY port is addressed for selection ending in the cycle and UT_ENB is deasserted. Once a MPHY port is selected, the cell transfer is accomplished as described by the cell-level handshake of UTOPIA Level 1. To operate an MPHY device in a single PHY environment, the address pins should be set to the value programmed by the management interface. Figure 7-1 shows an example where PHYs are polled until the end of a cell transmission cycle. The UT_CLAV signal shows that PHYs N - 3 and N + 3 can accept cells and that PHY N + 3 is selected. The PHY is selected with the rising clock edge 16. Immediately after the beginning of cell transmission to PHY N + 3, the ATM layer starts polling again. Up to 26 PHYs can be polled using the 2-clock polling cycles shown in Figure 7-1. This maximum value can only be reached if all responses occur in minimum delays, e.g., as the figure shows, where the response of the last PHY is obtained with clock edge 15, immediately followed by the UT_ENB pulse to the PHYs. If an ATM implementation needs additional clock cycles to select the PHY, fewer than 26 PHY can be polled during one cell cycle. Note that if the ATM decides to select PHY N again for the next cell transmission, it could leave the UT_ENB line asserted and start transmitting the next cell with clock edge 15. This results in back-to-back cell transmission. Note that the active PHY (PHY N) is polled in octet P48. According to the UTOPIA Level 1 specification, the PHY's UT_CLAV signal at this time indicates the possibility of a subsequent cell transfer. Polling of PHY N before octet P44 would be possible, but it does not indicate availability of the next cell.
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DS26102 16-Port TDM-to-ATM PHY Figure 7-2 shows an example where the transmission of cells through the transmit interface is stopped by the ATM, as no PHY is ready to accept cells. Polling then continues. Several clock cycles later one PHY gets ready to accept a cell. During the transmission pause the UT_DATA and UT_SOC may go into high-impedance state, as shown in Figure 7-2. UT_ENB is held in deasserted state. When a PHY is found that is ready to accept a cell (PHY_N + 3 in this case), the address of this PHY must be applied again to select it. This is necessary because of the 2-clock polling cycle, where the PHY is detected at clock edge 15. At this time, the address of PHY N + 3 is no longer on the bus, therefore, it must be applied again in the next clock cycle. PHY N + 3 is selected with clock edge 16.
Figure 7-1. Polling Phase and Selection Phase at Transmit Interface
SELECTION POLLING POLLING
UT_CLK UT_ADDR[4:0] UT_CLAV[0]
UT_ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N+1
1F
N-3
1F N-3
N-2
1F
N-1
1F
N+3
1F N+3
N+1
1F
N
1F N
N+3
1F N+3
N+1
1F
N-1
N+2
N-2
N-1
N+1
N+1
UT_DATA[7:0] UT_SOC
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
H1
H2
H3
H4
CELL XMIT TO:
PHY N
PHY N+3
Figure 7-2. End and Restart of Cell at Transmit Interface
DETECTION POLLING SELECTION POLLING
UT_CLK UT_ADDR[4:0] UT_CLAV[0]
UT_ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N+1
1F
N
1F
N+3
1F
N+2
1F
N-1
1F
N
1F
N+3
1F N+3
N+3
1F N+3
N-2
1F
N-3
N+1
N
N+3
N+2
N-1
N
N-2
UT_DATA[7:0] UT_SOC
P45
P46
P47
P48
H1
H2
H3
H4
CELL XMIT TO:
PHY N
PHY N+3
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DS26102 16-Port TDM-to-ATM PHY Figure 7-3 shows an example where the ATM must pause the data transmission, as it has no data available (in this case, for three clock cycles). This is done by deasserting UT_ENB and (optionally) setting UT_DATA and UT_SOC into high-impedance state. Polling may continue. In the last clock cycle, before restarting the transmission, the address "M" of the previously selected PHY is put on the UT_ADDR bus to reselect PHY M again.
Figure 7-3. Transmission to PHY Paused for Three Cycles
SELECTION POLLING POLLING
UT_CLK UT_ADDR[4:0] UT_CLAV[0]
UT_ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
N
1F N
N+1
1F N+1
N-4
1F N-4
M
1F M
N+2
1F N+2
N+3
1F N+3
UT_DATA[7:0] UT_SOC
P31 P32 P33 P34
P35 P36 P37 P38 P39
CELL XMIT TO:
PHY M
PAUSE XMIT
PHY M
7.2
UTOPIA-Side Transmit--Direct Status Mode (MULTITXCLAV)
The DS26102 supports direct status mode per af-phy-0039.000 for a maximum of four PHY ports connected to one ATM layer. For each PHY port, the status signals UR_CLAV and UT_CLAV are permanently available, according to UTOPIA Level 1 specification. PHY devices with up to four on-chip PHY ports have up to four UR_CLAV and up to four UT_CLAV status signals, one pair of UR_CLAV and UT_CLAV for each PHY port. Status signals and cell transfers are independent of each other. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. With respect to the status signals UR_CLAV and UT_CLAV, this mode of operation corresponds to that of four individual PHY devices, according to UTOPIA Level 1. With respect to the cell transfer, this mode of operation corresponds to that as described in other parts of this document. The ATM layer selects a PHY port for cell transfer by placing the desired port on the address lines (UR_ADDR[4:0], UT_ADDR[4:0]), while the enable signal (UR_ENB, UT_ENB) is deasserted. All PHY ports only examine the value on the address lines for possible selection when the enable signal is deasserted. In case the ATM suspends transmission for a specific PHY port during a cell transfer, no cells to/from other PHY ports can be transferred during this time. Figure 7-4 shows a direct status example for the transmit direction. Signals UT_CLAV[3:0] are associated with PHY port addresses 4, 3, 2, and 1. There is no need for a unique null device, therefore, "X = don't care" represents any address between 0 and 31 on the address lines UT_ADDR[4:0] or any data on the data bus. In this mode, the DS26102 supports address ranges 0 to 3, 8 to 11, 16 to 19, or 24 to 27. In Figure 7-4 the polling of PHY ports starts while no cell transfer takes place. The ATM layer has pending cells for all four PHY ports (one individual queue for each PHY port), but all four PHY ports cannot accept a cell. With rising clock edge 2, PHY port 1 indicates that it can accept a complete cell (UT_CLAV0 asserted). The ATM layer detects this at clock edge 3. It selects that PHY port by placing address 1 on the address lines with rising clock edge 3. PHY port 1 detects this at clock edge 4. At clock edge 5, PHY port 1 detects UT_ENB asserted, thus cell transfer for PHY port 1 starts with rising clock edge 5 (byte H1).
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DS26102 16-Port TDM-to-ATM PHY At clock edge 5, the ATM layer detects a cell available at PHY port 3 (UT_CLAV2 asserted). With rising clock edge 52, PHY port 1 indicates that it cannot accept an additional cell by deasserting UT_CLAV0. Thus, at clock edge 57, the ATM layer detects only UT_CLAV2 asserted (UT_CLAV1 and UT_CLAV3 remain deasserted). The ATM layer deselects PHY port 1 and selects PHY port 3 for cell transfer with rising clock edge 57 by placing address 3 on the address lines and deasserting UT_ENB. PHY port 1 and PHY port 3 detect this at clock edge 58. At clock edge 59, PHY port 3 detects UT_ENB asserted, thus cell transfer for PHY port 3 starts with rising clock edge 59 (byte H1). For additional examples, refer to ATM Forum document af-phy-0039.000.
Figure 7-4. Example of Direct Status Indication, Transmit Direction
UT_CLK UT_ADDR[4:0] UT_CLAV0 UT_CLAV1 UT_CLAV2 UT_CLAV3
UT_ENB
1
2
3
4
5
6
52
53
54
55
56
57
58
59
X PORT 1 PORT 2 PORT 3 PORT 4
1
X N-4
X = Don't Care
3
X
UT_SOC UT_DATA[7:0] X H1 H2 P44 P45 P46 P47 P48 Port 1 Transfer X H1 Port 3
7.3
Transmit Processing
The DS26102 can insert a valid HEC byte in the cell header, or it can be programmed to transparently transmit the HEC byte from ATM layer. When inserting a valid HEC byte, COSET (0x55) addition can be disabled. The 2 8 generator polynomial used is 1 + X + X + X . For idle/unassigned cell insertion (used for cell-rate decoupling), the DS26102 inserts a valid HEC byte with or without COSET addition, depending on the TCRDS (TCR1.3) microprocessor register bit. The DS26102 can scramble payload bytes, depending on the TPSE (TCR1.4) register 43 bit. The polynomial used for scrambling is X + 1. For debugging purposes, the DS26102 can be configured to introduce a single-bit HEC error in the cell header of transmitted cells. When configured in HEC error-insertion mode, the DS26102 inserts HEC errors in "HEC on period" number of cells and turns off HEC error insertion for "HEC off period" number of cells, as set in the transmit HEC error-pattern register (THEPR). This process repeats periodically until HEC error insertion is disabled through the THEIE bit (TCR1.1).
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DS26102 16-Port TDM-to-ATM PHY
Figure 7-5. Transmit Cell Flow and Processing
UTOPIA II Data Input
Unassigned Cell Idle Cell
Transmit FIFO
TCRDS (TCR1.3) HEC Insertion ON HEC Insertion ON/OFF THIE (TCR1.0) TCAE (TCR1.2)
TCAE (TCR1.2)
Payload Scrambling ON/OFF
TPSE (TCR1.4)
HOFFP[2:0] (THEPR)
HEC Error Insertion ON/OFF
THEIE (TCR1.1) HONP[4:0] (THEPR)
Cell Data to Framer (PHY)
7.4
Physical-Side Transmit
The transmit framer interface operates in one of two modes:
1) Gapped clock + data 2) Clock + data + frame-pulse indication
The mode can be selected on a per-port basis by the TPLIM control bit (TCR2.1). If configured in frame-pulseindication mode, valid data bits are not sent during frame-pulse positions in the case of T1 and during TS0 and TS16 positions in case of E1 direct mapping. The TS0 and TS16 locations are identified from the frame-pulse indication signal aligned with bit 0 of the E1 frame. The TPC (TCFR.0) bit determines T1 or E1 configuration. ATM cell octets are byte-aligned with respect to the frame-pulse-indication signal. In clear E1 mode, valid data bits are transmitted at every clock tick. The DS26102 can either output the frame-pulse signal or use it as an input as controlled through TFSD (TCR2.0). The active edge of the transmit clock can be selected through the TAES control bit (TCR2.2). The active edge used by the transmit interface should be configured to the opposite edge of that used by the external framer. Figure 7-6 shows the transmit-framer-interface operation in frame-pulse mode for T1. In this example, the DS26102 uses the positive edge of TCLK to launch TDATA and TFP. Bit B1 is the MSB of a valid cell octet and B8 is the LSB. The TFP signal should be aligned with the framing bit position. When interfacing to framers where the framing pulse and data active edges are individually configurable, it should be ensured that the sampling and updating should happen in opposite edges.
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DS26102 16-Port TDM-to-ATM PHY
Figure 7-6. Transmit Framer Interface in TFP Mode for T1
TCLK[x]1 TCLK[x]2 TFP[x]3 TDATA[x]
B190 B191 B192 F B1 B2 B3 B4 B5 B6 B7 B8 B9
1) TCLK negative edge active 2) TCLK positive edge active 3) TFP as input or output
DSO Channel 1
Figure 7-7 shows the transmit-framer-interface operation for T1 in gapped-clock mode. The framing overhead-bit position is gapped. In this diagram, DS26102 uses the positive edge to launch TDATA.
Figure 7-7. Transmit Framer Interface in Gapped-Clock Mode for T1
TCLK[x] TFP[x] TDATA[x]
B190 B191 B192 B1 TFP is Don't Care B2 B3 B4 B5 B6 B7 B8 B9
F-Bit Gapped
DSO Channel 1
Figure 7-8 shows the E1 transmit-framer-interface operation using TFP to indicate the beginning of the E1 frame. The DS26102 uses the positive edge to launch TDATA and TFP. Using TFP, the DS26102 identifies TS0 and TS16 slots and does not send valid data on TDATA in these slots. In this case, B0 to B7 are not valid data bits of a cell so that B8 is the MSB of the cell octet. The timing requirements for the TFP signal are the same as in the T1 case.
Figure 7-8. Transmit Framer Interface in TFP Mode for E1
TCLK[x]1 TCLK[x]2 TFP[x]3 TDATA[x]
B253 B254 B255 TS31 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 TS1
TS0 Slot
1) TCLK negative edge active 2) TCLK positive edge active 3) TFP as input or output (TFP_IN or TFP_OUT)
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DS26102 16-Port TDM-to-ATM PHY Figure 7-9 shows the transmit framer-interface operation for E1 in gapped-clock mode.
Figure 7-9. Transmit Framer Interface in Gapped-Clock Mode for E1
TCLK[x] TFP[x] TDATA[x]
B254 B255 TS31 TS0 (gapped) TFP is Don't Care B8 B9 TS1 B10
The fractional T1 (N x DS0) is supported in TFP and gapped-clock modes of the physical interface. In TFP mode, the framer must generate TFP during frame-overhead-bit and nonactive-DS0-channel positions. Fractional T1 is not supported if TFP is generated by the DS26102. In gapped-clock mode, TCLK should be gapped during frameoverhead-bit and nonactive-DS0-channel positions. In E1, to achieve a rate in multiples of 64kbps up to 2.048Mbps, the DS26102 should be configured in gapped-clock mode, and TCLK should be gapped during nonactive time slots. TFP mode (for both input and output TFP configurations) is not supported in fractional E1 configuration. The DS26102 can either use the T1/E1 clock from the framer or use an internally generated low-frequency clock at the transmit line interface. The low-frequency clock is the system clock (1/2 x GCLKIN) divided by 8. This clock is used primarily for diagnostic loopback. The TLICS bit (TCR2.6) selects between the framer clock and the internally generated clock. The internally generated clock should be used only in diagnostic loopback (otherwise, the framer and DS26102 are operating for different clocks). During diagnostic loopback, this clock is fed to the receive line interface unit.
8. RECEIVE OPERATION
The receive interface of the DS26102 is fully compliant to the ATM Forum's UTOPIA Level 2 specifications. Each octal block of the DS26102 can be configured to use one of the address ranges (0 to 7, 8 to 15, 16 to 23, and 24 to 30) as UTOPIA port addresses. If Rx FIFO is not empty, cell available is asserted. After cell transfer from a port, the external cell-available signal is updated based on the receive-FIFO fill level one clock cycle after cell transfer completion. During this one-clock cycle, cell-available indication for this port is kept in the deasserted state. In other words, one-clock minimum latency between two cell transfers from the same UTOPIA port is needed by the DS26102 to update its internal cell pointers. Section 8.3 gives additional details concerning the UTOPIA-side interface.
8.1
Physical-Side Receive 1) Gapped clock + data 2) Clock + data + frame-pulse indication
The receive framer interface operates in one of two modes:
The mode can be selected on a per-port basis with the receive physical-layer interface mode control bit (RPLIM) at RCR2.1. If configured in frame-pulse-indication mode, the bits coming at frame-pulse-indication positions are ignored in case of T1 direct mapping, and bits coming at TS0 and TS16 positions are ignored in case of E1 direct mapping. TS0 and TS16 slots are identified using the frame-pulse indication aligned with bit 0 of the E1 frame. The control bit RPC (RCFR.0) determines T1 or E1 configuration. If no frame-pulse indication is given, bits are sampled at every receive clock tick. If clear E1 operation is needed, the interface should be configured to operate in gapped 23 of 64
DS26102 16-Port TDM-to-ATM PHY clock + data mode, in which case the external frame-pulse-indication signal is ignored and the data bits are clocked at every clock tick. The active edge of the receive clock can be selected through the RAES (RCR2.2) control bit. The active edge selected for the Rx framer interface should be opposite the active edge that is used by the transmitting device (either an external framer or the transmit section of DS26102, when enabled for diagnostic loopback). Diagnostic loopback toward the ATM layer side (UTOPIA side) can be enabled through the DLBE (RCR2.0) control bit. In diagnostic loopback, data, clock, and frame-pulse indication generated by the transmit section of the DS26102 are used instead of the corresponding signals from the physical layer device. Rx physical-interface mode should be configured with same value as the Tx physical-interface mode. The Rx active-edge selection bit should be configured as the opposite edge of that used by the transmit section of the DS26102. Figure 8-1 shows the receive framer-interface operation for T1 mode with the DS26102 using the positive clock edge to sample RDATA and RFP and the framer using the negative edge to launch RDATA and RFP.
Figure 8-1. Receive Framer Interface in RFP Mode for T1
RCLK[x] RFP[x] RDATA[x]
B190 B191 B192 F B1 B2 B3 B4 B5 B6 B7 B8 B9
DSO Channel 1
Figure 8-2 shows the receive-framer-interface operation for T1 in gapped-clock mode. The framing overhead-bit position is gapped. In this figure, the DS26102 uses the positive edge to sample RDATA and RFP. RFP is don't care.
Figure 8-2. Receive Framer Interface in Gapped-Clock Mode for T1
RCLK[x] RDATA[x]
B190 B191 B192 B1 B2 B3 B4 B5 B6 B7 B8 B9
F-Bit Gapped
DSO Channel 1
Figure 8-3 shows the receive-framer-interface operation for E1 using RFP to indicate the beginning of the E1 frame. The DS26102 uses the positive edge of RCLK to sample RDATA and RFP. Using RFP, the DS26102 identifies TS0 and TS16 slots and ignores RDATA coming in these slots.
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DS26102 16-Port TDM-to-ATM PHY
Figure 8-3. Receive Framer Interface in RFP Mode for E1
RCLK[x] RFP[x] RDATA[x]
B253 B254 B255 TS31 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 TS1
TS0 Slot
Figure 8-4 shows the receive-framer-interface operation for E1 in gapped-clock mode. In this mode, RCLK is gapped during TS0 and TS16 locations.
Figure 8-4. Receive Framer Interface in Gapped-Clock Mode for E1
RCLK[x] RDATA[x]
B254 B255 TS31 Don't Care TS0 (gapped) B8 B9 TS1 B10
The fractional T1 (N x DS0) is supported in both RFP and gapped-clock modes of physical interface. In RFP mode, the framer must generate RFP during frame-overhead-bit and nonactive-DS0-channel positions. In gapped-clock mode, RCLK should be gapped during frame-overhead-bit and nonactive-DS0-channel positions. In E1 mode, the DS26102 should be configured in gapped-clock mode and RCLK should be gapped during nonactive time slots. RFP mode is not supported in fractional E1 configuration.
8.2
Receive Processing
The received bits, after ignoring framing-overhead bits, are checked for possible HEC pattern. The polynomial used 2 8 for HEC check is G(X) = 1 + X + X + X , per ITU I.432. Clearing the microprocessor interface register bit RCSE (RCR1.0) can disable the COSET subtraction (0x55). The cell boundaries in the incoming bit stream are identified based on HEC. Figure 8-5 shows the cell-delineation state machine. The cell-delineation state machine is initially in HUNT state. In HUNT state, it performs bit-by-bit hunting for correct HEC. If correct HEC is found, it transitions to the PRESYNC state where it checks cell-by-cell for correct HEC patterns. If DELTA-consecutive-correct patterns are received in PRESYNC, the cell-delineation state machine transitions to SYNC state. Otherwise, it goes to HUNT state and reinitiates bit-by-bit hunting. In SYNC state, if ALPHA-consecutive-incorrect HEC patterns are received, cell delineation is lost and it goes to HUNT state. In PRESYNC and SYNC states, only cell-by-cell checking for the proper HEC pattern is performed. For the DS26102, ALPHA = 7 and DELTA = 6. The persistence of the out-of-cell delineation (OCD) event is integrated into LCD, based on programmable integration time period (Rx-LCD integration-period register). If OCD persists for the programmed time, LCD is declared. LCD is deasserted only when cell delineation persists in SYNC for the same-programmed integration time. Whenever there is a change in LCD status (namely "into LCD" or "out of LCD"), an external interrupt is generated when enabled by the corresponding mask bit RCR2.4. The persistence is checked every system clock period (SYS_CLK) divided by 16,383. The default value of the Rx LCD integration-period register provides for an integration time of 100ms for a 16.5MHz SYS_CLK. 25 of 64
DS26102 16-Port TDM-to-ATM PHY
If single-bit header-error correction is enabled, the receiver mode of operation state machine follows the state machine given in Figure 8-6. Single-bit correction is done only if correction is enabled and the state machine is in the correction mode of operation at the start of cell transfer. Receiver mode of operation is valid only when cell delineation is in SYNC state. The DS26102 maintains 8-bit correctable and 12-bit uncorrectable HEC-errored cell counts. Both of these counters saturate.
Figure 8-5. Cell Delineation State Diagram
Bit by Bit Correct HEC
HUNT
ALPHA Consecutive Incorrect HEC
Incorrect HEC
PRESYNC
Cell by Cell
SYNC
Cell by Cell
DELTA Consecutive Correct HEC
Figure 8-6. Header Correction State Machine
Multibit Error Detected (Cell Discarded)
No Error Detected (No Action)
CORRECTION MODE
No Error Detected (No Action)
DETECTION MODE
Error Detected (Cell Discarded)
Single Bit Error Detected (Correction)
HEC error correction is performed based on receiver mode of operation. In correction mode, only single bit errors can be corrected and the receiver switches to detection mode. In detection mode, all cells with detected header errors are discarded, provided the receive-pass HEC-errored cells (RPHEC) control bit (RCR1.3) is clear. When a header is examined and found not to be in error, the receiver switches to correction mode. The term "no action" in Figure 8-6 means no correction is performed and no cell is discarded. The payload bytes of the cell are descrambled using the self-synchronizing descrambler polynomial 43 X + 1, as given in ITU-T I.432. The descrambling can be enabled through the RDE control bit (RCR1.2). Descrambling is activated if cell delineation is in PRESYNC or SYNC state. The cell header is not affected by descrambling.
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DS26102 16-Port TDM-to-ATM PHY After descrambling and single-bit header-error correction, the cells are written into the receive FIFO as long as cell delineation is in SYNC and the Rx FIFO is not full. Idle and/or unassigned cells can be filtered when enabled in the receive control registers. Uncorrectable HEC-errored cells are normally filtered and are not written into the Rx FIFO unless RPHEC (RCR1.3) is set. Note that if HEC error correction is disabled, all HEC-errored cells are termed as uncorrectable HEC-errored cells. A 16-bit counter tracks the number of cells that can be written into the Rx FIFO and saturates at 0xFFFF. Note that, whether or not the ATM layer dequeues cells from Rx FIFO, this counter is incremented if valid cells are received. This counter is cleared by the microprocessor interface once it is latched. A 4-cell buffer per port is maintained for rate decoupling.
8.3
UTOPIA-Side Receive--Muxed Mode with 1 RXCLAV
An internal version of the cell-available signal is maintained per port. The DS26102 drives the internal cell-available signals onto the external CLAV lines based on the configured polling mode. In direct status mode, only four ports are supported. The four external CLAV lines are driven with the corresponding internal CLAV signals for UTOPIA ports 0 to 3. In multiplexed-with-1-CLAV mode, only CLAV [0] is driven with the cell-available signal for the port corresponding to the current lower three UTOPIA address bits. The upper two UTOPIA address bits should match the configured address range. If cell transfer is going on for a port, its CLAV is kept asserted until the last byte is transferred to the ATM layer. This is accomplished to support interfacing with the octet-level ATM layer as well. The ATM layer must poll cell-available status for any fresh cell corresponding to a port only after the current cell transfer to the port is completed. The multiplexed with 1 CLAV polling-mode cycle is depicted in Figure 8-7, in which N, N + 2, N - 3, N - 2, N - 1, N + 3, N + 1 are considered part of the DS26102 UTOPIA ports. During reception of a cell from PHY N, the other PHYs are polled. It turns out that PHY N - 3 and PHY N + 3 have cells available, and PHY N + 3 is ultimately selected. Just like the transmit interface, the 2-clock polling cycle allows a maximum of 26 PHYs to be polled in the 8-bit mode during a cell transfer.
Figure 8-7. Polling Phase and Selection at Receive Interface
SELECTION POLLING POLLING
UR_CLK UR_ADDR[4:0] UR_CLAV[0]
UR_ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
N+2
1F N+2
N-3
1F N-3
N-2
1F N-2
N-1
1F N-1
N+3
1F N+3
N+1
1F N+1
N-1
1F N-1
N+3
1F N+3
N+1
1F N+1
N-1
UR_DATA[7:0] UR_SOC
P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48
H1
H2
H3
CELL RCV FROM:
PHY N
PHY N+3
Figure 8-8 shows a case when, after the end of transmission of a cell from PHY N, no other PHY has a cell available. Therefore, UR_ENB remains asserted as the ATM assumes a cell available from PHY N. With clock edge 9, PHY N also has no cell available, as UR_SOC remains low. The ATM then deasserts UR_ENB while the polling of the PHYs continues. With clock edge 15, PHY N - 3 is found to have a cell for transmission. So address N - 3 is applied, and the PHY N - 3 is selected with clock edge 16. Additional receive interface examples are available in ATM Forum's af-phy-0039.000. 27 of 64
DS26102 16-Port TDM-to-ATM PHY
Figure 8-8. End and Restart of Cell Transmission at Receive Interface
DETECTION POLLING SELECTION POLLING
UR_CLK UR_ADDR[4:0] UR_CLAV[0]
UR_ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N-3
1F N-3
N+1
1F N+1
N-1
1F N-1
N
1F N
N+3
1F N+3
N-1
1F N-1
N-3
1F N-3
N-3
1F N-3
N+1
1F N+1
N+2
UR_DATA[7:0] UR_SOC
P42 P43 P44 P45 P46 P47 P48
XX
H1
H2
H3
CELL RCV FROM:
PHY N
PHY N-3
8.4
UTOPIA-Side Receive--Direct Status Mode (MULTIRXCLAV)
Consider up to a maximum of four PHY ports connected to one ATM layer. For each PHY port, the status signals UR_CLAV and UT_CLAV are permanently available according to UTOPIA Level 1 specification. PHY devices with up to four on-chip PHY ports have up to four UR_CLAV and up to four UT_CLAV status signals, one pair of UR_CLAV and UT_CLAV for each PHY port. Status signals and cell transfers are independent of each other. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. With respect to the status signals UR_CLAV and UT_CLAV, this mode of operation corresponds to that of four individual PHY devices, according to UTOPIA Level 1. With respect to the cell transfer, this mode of operation corresponds to that described in this document and af-phy-0039.000. The ATM layer selects a PHY port for cell transfer by placing the desired port on the address lines (UR_ADDR[4:0], UT_ADDR[4:0]), while the enable signal (UR_ENB, UT_ENB) is deasserted. All PHY ports only examine the value on the address lines for possible selection when the enable signal is deasserted. If the ATM layer suspends transmission for a specific PHY port during a cell transfer, no cells to/from other PHY ports can be transferred during this time. Figure 8-9 shows an example for the receive direction. The status signals UR_CLAV[3:0] are associated with PHY port addresses 4, 3, 2, and 1. Note that for the DS26102, the address range can be any one of 0 to 3, 8 to 11, 16 to 19, and 24 to 27. There is no need for a unique null device, so "X = don't care" on the address lines UR_ADDR[4:0]. In Figure 8-9 the polling of PHY ports starts while no cell transfer takes place. The ATM layer monitors all four status signals UR_CLAV[3:0]. At clock edge 3, it detects a cell available at PHY port 1 (UR_CLAV0 asserted). It selects that PHY port by placing address 1 on the address lines with rising clock edge 3. PHY port 1 detects this at clock edge 4. At clock edge 5, PHY port 1 detects UR_ENB asserted, thus cell transfer for PHY port 1 starts with rising clock edge 5. At clock edge 5, the ATM layer detects a cell available at PHY port 3 (UR_CLAV2 asserted). Not knowing whether PHY port 1 may have another cell available or not, the ATM layer deselects PHY port 1 and selects PHY port 3 for cell transfer with rising clock edge 57 by placing address 3 on the address lines and deasserting UR_ENB. PHY port 1 and PHY port 3 detect this at clock edge 58. At clock edge 59, PHY port 3 detects UR_ENB asserted, thus cell transfer starts with rising clock edge 59. At clock edge 111, no cell is available at PHY ports 1, 2, and 4. The ATM layer keeps UR_ENB asserted and detects at clock edge 113 the first byte of another cell available from PHY port 3 (UR_CLAV2 asserted). Thus, cell transfer takes place starting with rising clock edge 112. At clock edge 164, again, no cell is available at PHY ports 1, 2, and 4. The ATM layer keeps the UR_ENB asserted and detects at 28 of 64
DS26102 16-Port TDM-to-ATM PHY clock edge 166 that there also is no cell available from PHY port 3 (UR_CLAV2 deasserted). Thus, the ATM layer deselects PHY port 3 by deasserting UR_ENB with rising clock edge 166.
Figure 8-9. Example Direct Status Indication, Receive Direction
1 2 3 4 5 6 57 58 59 60 111 112 113 114 164 165 166 167
UR_CLK UR_ADDR[4:0] UR_CLAV0 UR_CLAV1 UR_CLAV2 UR_CLAV3
UR_ENB
X PORT 1 PORT 2 PORT 3 PORT 4
1
X
3
X
X
X
UR_SOC UR_DATA[7:0] TRI-STATED H1 P48 H1 P48 H1 H2 P48 X
CELL TRANSFER (PORT 1)
CELL TRANSFER (PORT 3)
CELL TRANSFER (PORT 3)
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DS26102 16-Port TDM-to-ATM PHY
9. REGISTER MAPPING
The 8-bit registers described in this section are maintained per port, unless otherwise noted. Address bits [7:5] determine port number, address bit [4] distinguishes Tx and Rx section registers, and address bits [3:0] select the particular register in Tx and Rx sections. This register arrangement applies to each block of eight T1/E1 ports. The DS26102 contains two octal blocks that are selected with the BLS signal.
Table 9-A. Register Map
P1 00 -- 01 02 03 04 -- 05 -- 06 07 08 09 to 0F 10 -- 11 -- 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F P2 -- 20 21 22 23 -- 24 -- 25 26 27 -- 28 to 2F -- 30 -- 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F P3 -- 40 41 42 43 -- 44 -- 45 46 47 -- 48 to 4F -- 50 -- 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F P4 -- 60 61 62 63 -- 64 -- 65 66 67 -- 68 to 6F -- 70 -- 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F P5 -- 80 81 82 83 -- 84 -- 85 86 87 -- 88 to 8F -- 90 -- 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F P6 -- A0 A1 A2 A3 -- A4 -- A5 A6 A7 -- A8 to AF -- B0 -- B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF P7 -- C0 C1 C2 C3 -- C4 -- C5 C6 C7 -- C8 to CF -- D0 -- D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF P8 -- E0 E1 E2 E3 -- E4 -- E5 E6 E7 -- E8 to EF -- F0 -- F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF R/W RW -- W R R RW -- RW -- RW RW R -- RW RW -- W R R R R R R RW RW RW RW RW RW RW REGISTER TCFR -- TPCL TACC1 TACC2 TIUPB -- THEPR -- TCR1 TCR2 ISR -- RCFR RLCDIP -- RPCL RCHEC RUHEC1 RUHEC2 RACC1 RACC2 PSR RCR1 RCR2 RUFC RUFPM1 RUFPM2 RUFPM3 RUFPM4 FUNCTION Tx Configuration Register (Note 1) Reserved (Note 2) Tx PMON Counter Latch-Enable Register Tx-Assigned Cell Counter MSB (Note 3) Tx-Assigned Cell Counter LSB (Note 4) Tx Idle/Unassigned Payload Byte (Note 1) Reserved (Note 2) Tx HEC Error-Insertion Pattern (Note 1) Reserved (Note 2) Tx Control Register 1 Tx Control Register 2 Interrupt Status Register (Note 1) Reserved (Note 2) Rx Configuration Register (Note 1) Reserved Rx LCD Integration Register (Note 1) Reserved Rx PMON Counter-Latch Enable Rx Correctable HEC Latch Rx Uncorrectable HEC MSB Rx Uncorrectable HEC LSB Rx-Assigned Cell Counter MSB (Note 5) Rx-Assigned Cell Counter LSB (Note 6) Per Port Status Register Rx Control Register 1 Rx Control Register 2 Rx User-Filter Control Rx User-Filter Pattern/Mask 1 Rx User-Filter Pattern/Mask 2 Rx User-Filter Pattern/Mask 3 Rx User-Filter Pattern/Mask 4
P1 to P8 = Address locations (hex) for UTOPIA PHY port 1 through port 8. Note 1: These registers are common to all ports. Note 2: Writing into reserved address regions should be avoided. Reading from reserved address regions could give undefined value. Note 3: Tx-assigned cell counter MSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses. This register holds the upper 8-bit of the Tx-assigned-cell count for the port selected by accessing the Tx-PMON counter latch-enable register. Note 4: Tx-assigned cell counter LSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses. This register holds the lower 8-bit of the Tx-assigned cell count for the port selected by accessing the Tx-PMON counter latch-enable register. Note 5: Rx-assigned cell counter MSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses. This register holds the upper 8-bit of the Rx-assigned cell count for the port selected by accessing the Rx-PMON counter latch-enable register. Note 6: Rx-assigned cell counter LSB-latch register is an 8-bit register common to all ports. It can be accessed with any of the 8 addresses. This register holds the lower 8-bit of the Rx-assigned cell count for the port selected by accessing the Rx-PMON counter latch-enable register. Conventions: 1) In bit definitions, bit 7 is the most significant bit (MSB) and bit 0 is the least significant bit (LSB). 2) Ports can be referred with either 1 to 8 (one-based) or 0 to 7 (zero-based). While referring a port, the addressing system, either one-based or zero-based is explicitly mentioned in brackets.
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DS26102 16-Port TDM-to-ATM PHY
3) 4) Reserved bit fields should be replaced with 0 while writing and, upon reading, the value corresponding to reserved bit fields is undefined. R indicates read permission; W indicates write permission; RW indicates read/write permission for software to access a register.
10.
10.1
REGISTER DEFINITIONS
Transmit Registers
TCFR Transmit Configuration Register 00h (Common for All Transmit Ports) 6 -- 0 5 -- 0 4 -- 1 3 TADDR1 0 2 TADDR0 0 1 TPM 0 0 TPC 0
Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0
Bit 0: Transmit Port Configuration (TPC). This bit affects only the Tx section. 0 = T1 mode 1 = E1 mode Bit 1: Transmit Poll Mode (TPM). Transmit UTOPIA polling mode configuration. 0 = multiplexed with 1CLAV mode 1 = direct status Bits 2, 3: Transmit High Address (TADDR). These bits decide which upper 2 bits of the UTOPIA address are to be used by the ATM layer for selecting one of the ports. The lower 3 bits of address are assigned to the port number 1 to 8 (one-based): '00' for address range 0-7 '01' for address range 8-15 '10' for address range 16-23 * '11' for address range 24-30 Note that the address range selected when the BSL0 pin = 0 must be different than the address range selected when BSL0 = 1. Bits 3 to 7: Unassigned, read only
*Address 31 (1F hex) is reserved as the null address per UTOPIA forum. When an octal block is offset to the highest UTOPIA address range, the port at address 31 becomes inactive.
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DS26102 16-Port TDM-to-ATM PHY Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 TCR1 Transmit Control Register 1 06h, 26h, 46h, 66h, 86h, A6h, C6, E6h 6 TPEDIM 0 5 TPRS 0 4 TPSE 0 3 TCRDS 0 2 TCAE 1 1 THEIE 0 0 THIE 1
Bit 0: Transmit HEC Insertion Enable (THIE) 0 = HEC byte as received from the ATM layer is transparently passed. 1 = proper HEC value is computed and inserted into the HEC byte of the cell. Bit 1: Transmit HEC Error-Insertion Enable (THEIE) 0 = HEC error insertion disabled 1 = HEC errors are introduced into the transmitted cells, as specified by the transmit HEC error-insertion pattern register. Bit 2: Transmit COSET Addition Enable (TCAE) 0 = no COSET addition 1 = COSET (0x55) addition to the calculated HEC. Note that if HEC insertion is disabled, the HEC byte is transmitted transparently (this bit does not affect ATM layer cells). However, the HEC byte of idle/unassigned cells used for cell-rate decoupling includes COSET addition as long as the TCAE bit is enabled. Bit 3: Transmit Cell-Rate Decoupling Selection (TCRDS) 0 = idle cell 1 = unassigned cell Bit 4: Transmit Payload Scrambling Enable (TPSE) 0 = disable scrambling 1 = enable scrambling Bit 5: Transmit Parity Select (TPRS). This bit determines the parity mode expected on the UT_PAR signal. 0 = odd parity check selected for transmit UTOPIA bus 1 = even parity check selected for transmit UTOPIA bus Bit 6: Transmit Parity Error-Detect Interrupt Mask (TPEDIM) 0 = DS26102 does NOT generate an external interrupt on a Tx parity error. 1 = DS26102 does generate an external interrupt on a Tx parity error. Bit 7: Unassigned, must be set to 0 for proper operation
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DS26102 16-Port TDM-to-ATM PHY Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 TCR2 Transmit Control Register 2 07h, 27h, 47h, 67h, 87h, A7h, C7h, E7h 6 TLICS 0 5 FDC1 0 4 FDC0 0 3 TCES 0 2 TAES 0 1 TPLIM 0 0 TFSD 0
Bit 0: Transmit Frame-Sync Direction (TFSD) 0 = UTOPIA block accepts a transmit frame sync (TFP is an input). 1 = UTOPIA block generates a frame sync (TFP is an output). Bit 1: Transmit Physical-Layer Interface Mode (TPLIM) 0 = clock + data + frame-pulse-indication combination 1 = gapped clock + data combination Bit 2: Transmit Active-Edge Selection (TAES) 0 = positive edge of TCLK as timing reference 1 = negative edge of TCLK as timing reference Bit 3: Transmit Clear E1 Selection (TCES) 0 = channelized E1 (data at TS0 and TS16 is ignored) 1 = clear E1 (all E1 channels are used) Bits 4, 5: Transmit FIFO Depth Configuration Bits (FDC1, FDC0)
FDC1 0 0 1 1 FDC0 0 1 0 1 Cell Depth 4 3 2 Reserved
Bit 6: Transmit Line Interface Clock Selection (TLICS) 0 = The T1/E1 clock from the framer (TCLKx) is used at the transmit line interface. 1 = The internally generated system clock divided by 8 is used at the transmit line interface. Bit 7: Unassigned, must be set to 0 for proper operation Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 TPCL Transmit PMON Counter Latch 01h, 21h, 41h, 61h, 81h, A1h, C1h, E1h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0
Bits 0 to 7: The host should always write 0x00 to this register when latching the PMON counter. This register is provided for latching in the 16-bit transmit-assigned cell-count value of a port into the common transmitassigned cell-counter latch register. In order to read the transmit-assigned cell-count value, software writes into this register and then reads from the Tx-assigned cell counter MSB and LSB registers. A write into this register clears the value. Figure 10-1 depicts the sequence of operation for accessing the Tx-assigned cell counter (TACC) for a given port.
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DS26102 16-Port TDM-to-ATM PHY
Figure 10-1. Accessing Tx PMON Counter
WHAT THE HOST MUST DO
WRITE 00 INTO Tx-PMON COUNTER LATCH REGISTER (TPCL) FOR THE PORT WHOSE COUNTER VALUE IS TO BE OBTAINED. NOTE THAT ONLY THE ADDRESS SPECIFIC TO THE PORT INTENDED MUST BE USED.
HOW THE DS26101/DS26102 RESPONDS
DS26101/DS26102 LATCHES TX-ASSIGNED CELL-COUNTER VALUE OF THE PORT SELECTED INTO CORRESPONDING LATCH REGISTER AND CLEARS THE INTERNAL ASSIGNED CELL COUNTER OF THE PORT FOR FRESH ACCUMULATION.
READ FROM Tx-ASSIGNED CELL COUNTER LATCH REGISTER 1 (TACC1). NOTE THAT ANY ONE OF THE EIGHT ADDRESSES SPECIFIED FOR THIS REGISTER CAN BE USED.
DS26101/DS26102 DRIVES MOST SIGNIFICANT 8 BITS (TACC[15:8]) OF LATCHED ASSIGNED CELL-COUNT VALUE ONTO THE DATA BUS.
READ FROM Tx-ASSIGNED CELL COUNTER LATCH REGISTER 2 (TACC2). NOTE THAT ANY ONE OF THE EIGHT ADDRESSES SPECIFIED FOR THIS REGISTER CAN BE USED.
DS26101/DS26102 DRIVES LEAST SIGNIFICANT 8 BITS (TACC[7:0]) OF LATCHED ASSIGNED CELL-COUNT VALUE ONTO THE DATA BUS.
Register Name: Register Description: Register Address: Bit: Name: Default: 7 TACC15 0
TACC1 Transmit-Assigned Cell-Count Register 1 02h, 22h, 42h, 62h, 82h, A2h, C2h, E2h (Common to All Ports) 6 TACC14 0 5 TACC13 0 4 TACC12 0 3 TACC11 0 2 TACC10 0 1 TACC9 0 0 TACC8 0
Bits 0 to 7: Transmit-Assigned Cell Count (TACC8 to TACC15). This register is read-only. Register Name: Register Description: Register Address: Bit Name Default 7 TACC7 0 TACC2 Transmit-Assigned Cell-Count Register 2 03h, 23h, 43h, 63h, 83h, A3h, C3h, E3h (Common to All Ports) 6 TACC6 0 5 TACC5 0 4 TACC4 0 3 TACC3 0 2 TACC2 0 1 TACC1 0 0 TACC0 0
Bits 0 to 7: Transmit-Assigned Cell Count (TACC0 to TACC7). This register is read-only. These registers are common for all ports. For software convenience, any of the eight addresses can be used to access these registers. The transmit-assigned cell-count value reflects the number of ATM layer cells transmitted since last latching. For reading the 16-bit transmit-assigned cell count for a port, software must write into the transmit-PMON counter latchenable register for the desired port prior to reading these registers. Reading from these registers without writing into the latch-enable register returns the old value that was latched and not the current value.
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DS26102 16-Port TDM-to-ATM PHY Register Name: Register Description: Register Address: Bit: Name: Default: 7 TIUP7 0 TIUPB Transmit Idle/Unassigned Payload Byte Register 04h (Common for All Transmit Ports) 6 TIUP6 1 5 TIUP5 1 4 TIUP4 0 3 TIUP3 1 2 TIUP2 0 1 TIUP1 1 0 TIUP0 0
Bits 0 to 7: Transmit Idle/Unassigned Payload (TIUP0 to TIUP7). This register holds the payload byte to be carried in octets of idle/unassigned cells, transmitted toward the line for cell-rate decoupling. This register defaults to the value 6Ah. Register Name: Register Description: Register Address: Bit: Name: Default: 7 HOFFP4 0 THEPR Transmit HEC Error-Insertion Pattern Register 05h (Common for All Transmit Ports) 6 HOFFP3 0 5 HOFFP2 1 4 HOFFP1 0 3 HOFFP0 1 2 HONP2 0 1 HONP1 0 0 HONP0 1
Bits 0 to 2: HEC On Period (HONP0 to HONP2). This register holds the number of cells in which incorrect HEC (HEC error insertion is ON) is sent, if HEC error insertion is enabled. Bits 3 to 7: HEC Off Period (HOFFP0 to HOFFP4). This register holds the number of cells in which correct HEC (HEC error insertion is OFF) is sent, if HEC error insertion is enabled. If HEC error insertion in the transmit control register is enabled for a port (THEIE = 1), then for the "HEC off period" cells are transmitted to the port with correct HEC; for the "HEC on period" cells are sent with incorrect HEC. This cycle repeats until HEC error insertion is disabled. Note that HEC errors are inserted according to the above pattern as long as THEIE is set, whether HEC insertion (THIE) is enabled or not.
10.2
Status Registers
PSR Port Status Register 18h, 38h, 58h, 78h, 98h, B8h, D8h, F8h 6 TPED 0 5 CDS1 0 4 CDS0 0 3 RMS 0 2 LCDS 1 1 LCDCSIS 0 0 FOIS 0
Register Name: Register Description: Register Address: Bit: Name: Default: 7 EXSTAT 0
Bit 0: Receive FIFO-Overrun Interrupt Status (FOIS). This status bit is set when the receive FIFO overruns. It creates an interrupt on the INT pin if the Rx FIFO-overrun interrupt mask bit (RCR2.3) is set. This bit is reset when read. Bit 1: LCD Change-of-State Interrupt Status (LCDCSIS). This status bit is set when LCD status changes. It creates an interrupt on the INT pin if the LCD interrupt mask bit (RCR2.4) is set. This bit is reset when read. Bit 2: LCD Status (LCDS). The LCDS bit indicates the current status of LCD. 0 = in-cell delineation 1 = loss-of-cell delineation Bit 3: Receiver Mode Status (RMS). This bit shows valid status only when HEC correction is enabled. 0 = correction mode 1 = detection mode
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DS26102 16-Port TDM-to-ATM PHY Bits 4, 5: Cell Delineation Status 0, 1 (CDS0, CDS1). These bits show the cell delineation status. Bit 5 indicates instantaneous OCD status.
CDS1 0 0 1 CDS0 0 1 x Cell Delineation Status HUNT State PRESYNC State SYNC State
Bit 6: Transmit Parity Error Detect (TPED). This bit is set for each transmit parity error that is detected on the transmit UTOPIA interface. It can generate an interrupt when enabled by TPEDIM in TCR1. This bit is reset if read access to this register is detected. Bit 7: External Status Event (EXSTAT). This bit is set on the rising edge of the signal applied to the associated EXSTAT signal. It can generate an interrupt when enabled by EXSTATIM in RCR2. This bit is reset if read access to this register is detected. EXSTAT1 maps to this bit in the PSR for port 1 (18h) up to EXSTAT8, which maps to the PSR for port 8 (F8h). A typical application might connect the 1SECOUT signal created by the DS26102 to one of the EXSTAT signals so that an interrupt can be created on 1-second boundaries. The EXSTAT signals, however, can also be used to provide microprocessor access to board-level hardware-status pins or an off-chip interval timer. Register Name: Register Description: Register Address: Bit: Name: Default: 7 PSR8 0 ISR Interrupt Status Register 08h (Common for All Ports) 6 PSR7 0 5 PSR6 0 4 PSR5 0 3 PSR4 0 2 PSR3 0 1 PSR2 0 0 PSR1 0
The ISR register reports which of the 8 ports are currently generating interrupts. ISR.0 reports the status for port 1 (18h), while ISR.7 reports the status for port 8 (F8h). When the associated port's status register is read (and consequently cleared), the associated bit in this register is also cleared. Note that only status bits that are enabled to generate an interrupt (i.e., the interrupt mask bit is set) set the reporting bit in this register.
10.3 Receive Registers
Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 RCFR Receive Configuration Register 10h (Common for All Receive Ports) 6 -- 0 5 -- 0 4 -- 1 3 RADDR1 0 2 RADDR0 0 1 RUPM 0 0 RPC 0
Bit 0: Receive Port Configuration (RPC). This bit affects only the Rx section. 0 = T1 mode 1 = E1 mode Bit 1: Receive Polling Mode (RUPM) 0 = multiplexed with 1CLAV mode 1 = direct status Bits 2, 3: Receive High Address (RADDR). These bits decide which upper 2 bits of the UTOPIA address are to be used by the ATM layer for selecting one of the ports. The lower 3 bits of address are assigned to port number 1 to 8 (one-based): '00' for address range 0-7 '01' for address range 8-15 36 of 64
DS26102 16-Port TDM-to-ATM PHY '10' for address range 16-23 * '11' for address range 24-30 Note that the address range selected when the BSL0 pin = 0 must be different than the address range selected when BSL0 = 1. Bits 4 to 7: Unassigned, read only
*Address 31 (1F hex) is reserved as the null address per UTOPIA forum. When an octal block is offset to the highest UTOPIA address range, the port at address 31 becomes inactive.
Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0
RCR1 Receive Control Register 1 19h, 39h, 59h, 79h, 99h, B9h, D9h, F9h 6 RPRS 0 5 RUCFE 0 4 RICFE 0 3 RPHEC 0 2 RDE 0 1 RHECE 0 0 RCSE 1
Bit 0: Receive COSET Subtraction Enable (RCSE) 0 = DS26102 does NOT do COSET subtraction from HEC byte for checking HEC. 1 = DS26102 subtracts COSET polynomial (0x55) from the HEC byte for checking HEC. Bit 1: Receive HEC Error-Correction Enable (RHECE) 0 = single-bit HEC error correction is disabled. 1 = The DS26102 corrects single-bit HEC errors based on the current state of receiver mode of operation. Single-bit error correction is done only if this bit is set and the receiver mode of operation is in CORRECTION state. Bit 2: Receive Descrambling Enable (RDE) 0 = payload descrambling is disabled. 1 = payload descrambling is enabled. Payload of cells received in the PRESYNC and SYNC states of cell 43 delineation are descrambled, based on the self-synchronizing polynomial X + 1. The cell header is unaffected by descrambling. Bit 3: Receive Pass HEC-Errored Cells (RPHEC) 0 = DS26102 passes only error-free and error-corrected cells to the ATM layer. 1 = DS26102 passes all received cells, including HEC errored cells to the ATM layer when cell delineation is in SYNC. Bit 4: Receive Idle Cell-Filter Enable (RICFE) 0 = DS26102 does NOT filter idle cells. 1 = DS26102 filters all idle cells received from being written into receive FIFO. The cell header of idle cell (first 5 bytes) is 0x00, 0x00, 0x00, 0x01, and proper HEC byte. Cell payload is not considered for idle cell filtering. Bit 5: Receive Unassigned Cell-Filter Enable (RUCFE) 0 = DS26102 does NOT filter unassigned cells. 1 = DS26102 filters all unassigned cells received from being written into receive FIFO. The cell header of unassigned cell (first five bytes) is 0x00, 0x00, 0x00, 0x00 and proper HEC byte. Cell payload is not considered for unassigned cell filtering.* Bit 6: Receive Parity Select (RPRS). This bit determines the parity type for the UR_PAR signal. 0 = odd parity calculated for receive UTOPIA bus 1 = even parity calculated for receive UTOPIA bus Bit 7: Unassigned, must be set to 0 for proper operation
*The header pattern of an unassigned cell is 0x00, 0x00, 0x00, 0x00, and proper HEC byte. The header pattern of an idle cell is 0x00, 0x00, 0x00, 0x01, and proper HEC byte for the first 4 bytes. Note that, for cell filtering, only the header pattern (payload is don't care) is checked.
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DS26102 16-Port TDM-to-ATM PHY Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 RCR2 Receive Control Register 2 1Ah, 3Ah, 5Ah, 7Ah, 9Ah, BAh, DAh, FAh 6 -- 0 5 EXSTATIM 0 4 LCDIM 0 3 RFOIM 0 2 RAES 0 1 RPLIM 0 0 DLBE 0
Bit 0: Diagnostic Loopback Enable (DLBE) 0 = normal operation 1 = diagnostic loopback is enabled. In this loopback, the transmit data and clock is looped back onto the receive side. The Rx physical interface mode should be configured with the same value as the Tx physical interface mode. The Rx active-edge selection bit should be configured as the opposite edge of that used by the transmit section of the DS26102. It is possible to use the internally generated SYS_CLK/8 in place of TCLK for this mode, enabled with (TCR2.6). Bit 1: Receive Physical-Layer Interface Mode (RPLIM) 0 = clock + data + frame-pulse combination 1 = gapped clock + data combination Bit 2: Receive Active Clock-Edge Selection (RAES) 0 = positive edge of receive line clock is used for sampling input line signals. 1 = negative edge of receive line clock is used for sampling. Bit 3: Receive FIFO Overrun Interrupt Mask (RFOIM) 0 = DS26102 does NOT generate an external interrupt for receive FIFO-overrun events. 1 = DS26102 generates an external interrupt if a receive FIFO-overrun condition has occurred. Bit 4: LCD Interrupt Mask (LCDIM) 0 = DS26102 does NOT generate external interrupt for LCD state changes. 1 = DS26102 does generate an external interrupt if the LCD state has changed. Bit 5: External Status Event Interrupt Mask (EXSTATIM) 0 = DS26102 does NOT generate an external interrupt on the EXSTAT signal. 1 = DS26102 generates an external interrupt on the rising edge of the EXSTAT signal associated with the enabled port. Bits 6, 7: Unassigned, must be set to 0 for proper operation
10.3.1 Additional Receive Control Information
The active edge of the line clock used for sampling the input signals from the physical layer, namely data and frame-pulse-indication signals, are programmed to use the opposite edge of the active edge, which is used by the physical layer (framer). For example, if the physical layer uses the positive edge of the receive line clock to launch data and frame-pulse-indication signals, then the receive active-line clock-edge selection bit is programmed to 1, so that the receive line interface block uses the negative edge to sample the incoming signals. In diagnostic loopback, the receive active-line clock edge is programmed to use the opposite edge as that of the transmit interface. So, the receive active-line clock-edge selection (RAES) is programmed inverted from the transmit activeline clock-edge selection (TAES) during diagnostic loopback. The receive physical-layer interface mode determines the protocol used in the receive interface for sampling data bits. In gapped clock and data combination, the data bits are sampled at every line clock. The receive line clock is gapped at the framing-overhead-bit location. In clock, data, and frame-pulse-indication combination, data bits coming with frame-pulse indication asserted are ignored in the T1 case. In the E1 case, frame-pulse indication is used to locate TS0 and TS16 slots, and data bits coming at these time slots are ignored. In the clear E1 case, the interface should be configured in gapped clock and data combination even though the clock may not be gapped. 38 of 64
DS26102 16-Port TDM-to-ATM PHY For clear E1, data bits are sampled by the receive section at every clock tick, and the external frame-pulse indication is ignored. The receive FIFO-overrun condition indicates that the receive FIFO has been filled with 4 cells before the ATM layer has read the FIFO. The four cells that caused the receive FIFO-overrun condition remain intact in the receive FIFO, and subsequent cells are not written into memory until the ATM layer reads at least one cell through the UTOPIA II interface. Register Name: Register Description: Register Address: Bit: Name: Default: 7 RLIP7 0 RLCDIP Receive LCD Integration Period 11h (Common for All Receive Ports) 6 RLIP6 1 5 RLIP5 1 4 RLIP4 0 3 RLIP3 0 2 RLIP2 1 1 RLIP1 1 0 RLIP0 0
Bits 0 to 7: Receive LCD Integration Period (RLIP0 to RLIP7). This 8-bit register holds the value of the LCD integration period (the time the cell delineation condition must persist before the DS26102 declares LCD). The DS26102 also deasserts the LCD indication once cell delineation is maintained in the SYNC state for the amount of time programmed in this register. LCD state-change condition can be programmed to generate an external interrupt through RCR2.4. A value of 0 programmed into this register declares LCD for every OCD condition at the resolution of the internal system clock period x 16,383. The value to be used in this register can be determined as follows: Register value to be programmed = (Integration time needed) / (System clock period x 16,383) E.g., for a system clock period of 60ns and desired integration time of 100ms, the register value should be: 100,000,000ns / (60ns x 16,383) = 66h Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 RPCL Receive-PMON Counter Latch Enable 12h, 32h, 52h, 72h, 92h, B2h, D2h, F2h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0
Bits 0 to 7: The host should always write 0x00 to this register when latching the receive PMON counter. Writing 0x00 to this register latches all receive-PMON counter values for the given port. Namely, the 16-bit receiveassigned cell-count value, 12-bit receive uncorrectable HEC-count value, and 8-bit receive correctable HEC-count value of a port is latched into the associated registers. A write into this register also clears the receive PMON counters for that port. Figure 10-2 depicts the sequence of operation to be performed for accessing Rx PMON counters for a port. For example, if port 8's (one-based) Rx-assigned cell-count value is to be read, software must first write into RxPMON counter-latch enable register at 0xF2 and then read from Rx-assigned cell counter MSB-latch register at 0xF6 and Rx-assigned cell counter LSB register at 0xF7. Note that all Rx PMON counters maintained for port 8 are reset as the RPCL register is accessed. Thus, it is recommended that all Rx PMON counters be read together by following the sequence depicted in Figure 10-2.
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DS26102 16-Port TDM-to-ATM PHY
Figure 10-2. Accessing Rx PMON Counters
WHAT THE HOST MUST DO
WRITE 00 INTO Rx-PMON COUNTER LATCHENABLE REGISTER (RPCL) FOR THE PORT WHOSE COUNTER VALUES ARE TO BE OBTAINED. NOTE THAT ONLY THE ADDRESS SPECIFIC TO THE INTENDED PORT IS USED.
HOW THE DS26101/DS26102 RESPONDS
DS26101/DS26102 LATCH ALL RX PMON COUNTER VALUES OF THE PORT SELECTED INTO CORRESPONDING LATCH REGISTERS AND CLEAR ALL INTERNAL PMON COUNTERS OF THE PORT FOR FRESH ACCUMULATION.
READ FROM Rx-CORRECTABLE HEC COUNTER LATCH REGISTER (RCHEC). NOTE THAT ANY ONE OF THE EIGHT ADDRESSES SPECIFIED CAN BE USED.
DS26101/DS26102 DRIVE LATCHED CORRECTABLE HEC COUNT VALUE (RCHEC[7:0]) INTO THE MICROPROCESSOR DATA BUS.
READ FROM Rx-UNCORRECTABLE HEC COUNTER MSB LATCH REGISTER (RUHEC1). NOTE THAT ANY ONE OF THE EIGHT ADDRESSES SPECIFIED CAN BE USED.
DS26101/DS26102 DRIVE THE FOUR MOST SIGNIFICANT BITS OF THE LATCHED UNCORRECTABLE HEC COUNT VALUE (RUHEC[11:8]) ONTO THE DATA BUS.
READ FROM Rx-UNCORRECTABLE HEC COUNTER LSB LATCH REGISTER (RUHEC2). NOTE THAT ANY ONE OF THE EIGHT ADDRESSES SPECIFIED CAN BE USED.
DS26101/DS26102 DRIVE THE LEAST SIGNIFICANT 8 BITS OF THE LATCHED UNCORRECTABLE HEC COUNT VALUE (RUHEC[7:0]) ONTO THE DATA BUS.
READ FROM Rx-ASSIGNED CELL COUNTER MSB LATCH REGISTER (RACC1). NOTE THAT ANY ONE OF THE EIGHT ADDRESSES SPECIFIED CAN BE USED.
DS26101/DS26102 DRIVE THE MOST SIGNIFICANT 8 BITS OF THE ASSIGNED CELL-COUNT VALUE (RACC[15:8]) ONTO THE DATA BUS.
READ FROM Rx-ASSIGNED CELL COUNTER LSB LATCH REGISTER (RACC2). NOTE THAT ANY ONE OF THE EIGHT ADDRESSES SPECIFIED CAN BE USED.
DS26101/DS26102 DRIVE THE LEAST SIGNIFICANT 8 BITS OF THE ASSIGNED CELL-COUNT VALUE (RACC[7:0]) ONTO THE DATA BUS.
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DS26102 16-Port TDM-to-ATM PHY Register Name: Register Description: Register Address: Bit: Name: Default: 7 RCHC7 0 RCHEC Receive Correctable-HEC Counter 13h, 33h, 53h, 73h, 93h, B3h, D3h, F3h (Common to All Ports) 6 RCHC6 0 5 RCHC5 0 4 RCHC4 0 3 RCHC3 0 2 RCHC2 0 1 RCHC1 0 0 RCHC0 0
Bits 0 to 7: Receive Correctable-HEC Counter (RCHC0 to RCHC7). This register holds the number of correctable HEC-errored cells received since the last latching. Note that this count corresponds to cells received when cell delineation is in SYNC. A correctable HEC-errored cell is a cell with single-bit error, provided single-bit HEC error correction is enabled through RCR1.1 and the receiver mode of operation is in correction mode. Correctable-HEC count value is not affected if HEC-error correction is disabled. Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 RUHEC1 Receive Uncorrectable-HEC Counter Register 1 14h, 34h, 54h, 74h, 94h, B4h, D4h, F4h (Common to All Ports) 6 -- 0 5 -- 0 4 -- 0 3 RUHC11 0 2 RUHC10 0 1 RUHC9 0 0 RUHC8 0
Bits 0 to 3: Receive Uncorrectable-HEC Counter (RUHC8 to RUHC11) Bits 4 to 7: Unused Register Name: Register Description: Register Address: Bit: Name: Default: 7 RUHC7 0 RUHEC2 Receive Uncorrectable-HEC Counter Register 2 15h, 35h, 55h, 75h, 95h, B5h, D5h, F5h (Common to All Ports) 6 RUHC6 0 5 RUHC5 0 4 RUHC4 0 3 RUHC3 0 2 RUHC2 0 1 RUHC1 0 0 RUHC0 0
Bits 0 to 7: Receive Uncorrectable-HEC Counter (RUHC0 to RUHC7). The RUHEC1 and RUHEC2 registers count the number of uncorrectable HEC-errored cells received since the last latching. Note that this count corresponds to cells received when cell delineation is in SYNC. For every SYNC-to-HUNT transition of the cell delineation state machine, the "Correctable + Uncorrectable" error-count value increases by 6 instead of 7. If HEC correction is enabled, for every SYNC-to-HUNT transition, the correctable HEC count increases by 1 and the uncorrectable HEC count increases by 5. If HEC correction is disabled, correctable HEC count is not affected and uncorrectable HEC count increases by 6. Note that upon the reception of the 7th consecutive HEC pattern, cell delineation goes to HUNT state. Receive PMON counters are not updated when cell delineation is out of SYNC state. Note that write access to the RPCL register latches internal receive-PMON values and clear the counters. Uncorrectable HEC-error cell means:
If HEC-error correction is enabled (RHECE = 1) { Cell with multibit HEC error in cell header OR Cell with single-bit HEC error in cell header, provided receiver mode of operation is in detection mode } else { Cell with either single bit or multibit HEC error in cell header }
Note that this count corresponds to cells received when cell delineation is in SYNC.
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DS26102 16-Port TDM-to-ATM PHY Register Name: Register Description: Register Address: Bit: Name: Default: 7 RACC15 0 RACC1 Receive-Assigned Cell-Count Register 1 16h, 36h, 56h, 76h, 96h, B6h, D6h, F6h (Common to All Ports) 6 RACC14 0 5 RACC13 0 4 RACC12 0 3 RACC11 0 2 RACC10 0 1 RACC9 0 0 RACC8 0
Bits 0 to 7: Receive-Assigned Cell Count 8 to 15 (RACC8 to RACC15) Register Name: Register Description: Register Address: Bit: Name: Default: 7 RACC7 0 RACC2 Receive-Assigned Cell-Count Register 2 17h, 37h, 57h, 77h, 97h, B7h, D7h, F7h (Common to All Ports) 6 RACC6 0 5 RACC5 0 4 RACC4 0 3 RACC3 0 2 RACC2 0 1 RACC1 0 0 RACC0 0
Bits 0 to 7: Receive-Assigned Cell Count 0 to 7 (RACC0 to RACC7). The RACC1 and RACC2 registers are common registers for all ports. For software convenience, any of the eight addresses can be used to access these registers. For reading the 16-bit receive-assigned cell count for a port, software must write into the RPCL register for the port before reading from these registers. Reading from these registers without writing into the latch-enable register returns the old value that was latched and not the current value of the receive-assigned cell count of a port. The assigned cell-count value reflects the number of cells written into the receive FIFO that can be read by the ATM layer since last latching. Note that, whether or not the ATM layer dequeues cells from the receive FIFO, the assigned cell counter of a port is incremented upon the reception of a valid ATM layer cell, as long as the cell delineation is in SYNC state. A valid ATM layer cell is defined as:
If (HEC-errored cells are programmed to be passed to ATM layer (RPHEC = 1)) { Cell received when cell delineation is in SYNC state } else { Cell with correct HEC OR if (HEC-error correction is enabled (RHECE=1)) { Cell with single-bit HEC error in cell header, provided receiver mode is in correction } }
Note that this count corresponds to cells received when cell delineation is in SYNC.
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DS26102 16-Port TDM-to-ATM PHY
10.3.2 User-Programmable Cell Filtering
User-programmable cell filtering allows the user to define a maskable pattern for each of the 4 bytes in the cell header so that the DS26102 either filters (rejects) all matching receive cells, or alternately only accepts cells that match the predefined pattern. Five registers are defined for this function per port. This function is an addition to the DS26102's ability to filter standard idle/unassigned cells. The user must program a filter pattern in the RUFPM1-4 registers by setting the UFPMS (RUFC.2) bit = 0, then program the mask, or "don't care" pattern, in the RUFPM1-4 registers by setting the UFPMS bit = 1. Register Name: Register Description: Register Address: Bit: Name: Default: 7 -- 0 RUFC Receive User-Filter Control 1Bh, 3Bh, 5Bh, 7Bh, 9Bh, BBh, DBh, FBh 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 UFPMS 0 1 UFMS 0 0 UFEN 0
Bit 0: User-Filter Enable (UFEN) 0 = do not apply the user-defined filter. 1 = filter incoming cells based on the UFPM registers Bit 1: User-Filter-Mode Select (UFMS) 0 = reject (block) all cells that match the user-defined pattern and mask. 1 = accept (pass) only the cells that match the user-defined pattern and mask. Bit 2: User-Filter Pattern/Mask Select (UFPMS). This bit must be set = 0 to enter the filter pattern, and then set = 1 to enter the filter mask. 0 = user-filter pattern/mask (UFPM) registers are enabled as pattern mode. 1 = user-filter pattern/mask (UFPM) registers are enable as mask mode. Bits 3 to 7: Unassigned, must be set to 0 for proper operation Register Name: Register Description: Register Address: Bit: Name: Default: 7 H1.7 0 RUFPM1 Receive User-Filter Pattern/Mask Register 1 1Ch, 3Ch, 5Ch, 7Ch, 9Ch, BCh, DCh, FCh 6 H1.6 0 5 H1.5 0 4 H1.4 0 3 H1.3 0 2 H1.2 0 1 H1.1 0 0 H1.0 0
Bits 0 to 7: Receive User-Filter Pattern/Mask 1 (UFPM1[7:0]). When UFPMS = 0, this register can be programmed with the cell header pattern to match with the first octet (H1) of the received ATM cell. When UFPMS = 1, this register can be programmed with cell header mask associated with the first octet (H1). A logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. An FFh in this register enables matching of all 8 bits in pattern register 1. A logic 0 causes the masking of the corresponding bit (essentially a don't care in the match).
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DS26102 16-Port TDM-to-ATM PHY Register Name: Register Description: Register Address: Bit: Name: Default: 7 H2.7 0 RUFPM2 Receive User-Filter Pattern/Mask Register 2 1Dh, 3Dh, 5Dh, 7Dh, 9Dh, BDh, DDh, FDh 6 H2.6 0 5 H2.5 0 4 H2.4 0 3 H2.3 0 2 H2.2 0 1 H2.1 0 0 H2.0 0
Bits 0 to 7: Receive User-Filter Pattern/Mask 2 (UFPM2[7:0]). When UFPMS = 0, this register can be programmed with the cell header pattern to match with the second octet (H2) of the received ATM cell. When UFPMS = 1, this register can be programmed with the cell header mask associated with the second octet (H2). A logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. An FFh in this register enables matching of all 8 bits in pattern register 2. A logic 0 causes the masking of the corresponding bit (essentially a don't care in the match). Register Name: Register Description: Register Address: Bit: Name: Default: 7 H3.7 0 RUFPM3 Receive User-Filter Pattern/Mask Register 3 1Eh, 3Eh, 5Eh, 7Eh, 9Eh, BEh, DEh, FEh 6 H3.6 0 5 H3.5 0 4 H3.4 0 3 H3.3 0 2 H3.2 0 1 H3.1 0 0 H3.0 0
Bits 0 to 7: Receive User-Filter Pattern/Mask 3 (UFPM3[7:0]). When UFPMS = 0, this register can be programmed with the cell header pattern to match with the third octet (H3) of the received ATM cell. When UFPMS = 1, this register can be programmed with the cell header mask associated with the third octet (H3). A logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. An FFh in this register enables matching of all 8 bits in pattern register 3. A logic 0 causes the masking of the corresponding bit (essentially a don't care in the match). Register Name: Register Description: Register Address: Bit: Name: Default: 7 H4.7 0 RUFPM4 Receive User-Filter Pattern/Mask Register 4 1Fh, 3Fh, 5Fh, 7Fh, 9Fh, BFh, DFh, FFh 6 H4.6 0 5 H4.5 0 4 H4.4 0 3 H4.3 0 2 H4.2 0 1 H4.1 0 0 H4.0 0
Bits 0 to 7: Receive User-Filter Pattern/Mask 4 (UFPM4[7:0]). When UFPMS = 0, this register can be programmed with the cell header pattern to match with the fourth octet (H4) of the received ATM cell. When UFPMS = 1, this register can be programmed with the cell header mask associated with the fourth octet (H4). A logic 1 in any mask bit enables the comparison of the corresponding pattern bit to the header bit. An FFh in this register enables matching of all 8 bits in pattern register 4. A logic 0 causes the masking of the corresponding bit (essentially a don't care in the match).
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DS26102 16-Port TDM-to-ATM PHY
11.
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS26102 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE (Table 11-A). The DS26102 contains the following functions, as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register
The TAP has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details.
Figure 11-1. JTAG Functional Block Diagram
BOUNDRY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER TEST ACCESS PORT CONTROLLER SELECT OUTPUT ENABLE
MUX
VDD
10k
VDD
10k
VDD
10k
JTDI
JTMS
JTCLK
JTRST
JTDO
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DS26102 16-Port TDM-to-ATM PHY TAP Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 11-2). Test-Logic-Reset. Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. Run-Test-Idle. The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test registers remain idle. Select-DR-Scan. All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state. Capture-DR. Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is LOW or it goes to the Exit1-DR state if JTMS is HIGH. Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. Exit1-DR. While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the PauseDR state. Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain their previous state. The controller remains in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH puts the controller in the Exit2-DR state. Exit2-DR. A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state and terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state. Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output because of changes in the shift register. Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the Shift-IR state. Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK toward the serial output. The parallel register as well as all test registers remains at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW keeps the controller in the Shift-IR state while moving data one stage thorough the instruction shift register. Exit1-IR. A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK puts the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK. 46 of 64
DS26102 16-Port TDM-to-ATM PHY Exit2-IR. A rising edge on JTCLK with JTMS LOW puts the controller in the Update-IR state. The controller loops back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state. Update-IR. The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the Run-Test-Idle state. With JTMS HIGH, the controller enters the Select-DR-Scan state.
Figure 11-2. TAP Controller State Diagram
1 Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 1 0 1
0
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DS26102 16-Port TDM-to-ATM PHY
11.1
Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH moves the controller to the Update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26102 and its respective operational binary codes are shown in Table 11-A.
Table 11-A. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001
SAMPLE/PRELOAD. This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register through JTDI using the Shift-DR state. BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device's normal operation. EXTEST. This instruction allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs of all digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR samples all digital inputs into the boundary scan register. CLAMP. All digital outputs of the device output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction. HIGHZ. All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected between JTDI and JTDO. IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code is loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
Table 11-B. ID Code Structure
MSB Version--Contact Factory 4 Bits Device ID See Table 11-C JEDEC 00010100001 LSB (Must be 1) 1 1
Table 11-C. Device ID Codes
PART DS26102 ID CODE 0000000000100111
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11.2
Test Registers
IEEE 1149.1 requires a minimum of two test registers--the bypass register and the boundary scan register. An optional test register, the identification register, has been included with the DS26102 design. It is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Bypass Register. This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions. It provides a short path between JTDI and JTDO. Boundary Scan Register. This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells. It is n bits in length. See Table 11-D for the cell bit locations and definitions. Identification Register. The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state.
Table 11-D. Boundary Scan Control Bits
CELL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NAME -- TFP13 TFP13 TCLK13 TDATA13 -- TFP12 TFP12 TCLK12 TDATA12 -- TFP11 TFP11 TCLK11 TDATA11 -- TFP10 TFP10 TCLK10 TDATA10 -- TFP9 TFP9 TCLK9 TDATA9 -- TFP8 TFP8 TCLK8 TDATA8 RFP15 RCLK15 RDATA15 RFP14 RCLK14 RDATA14 RFP13 RCLK13 RDATA13 RFP12 RCLK12 TYPE controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only CONTROL CELL 0 161 5 161 10 161 15 161 20 161 25 161 CELL 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 NAME RDATA12 RFP11 RCLK11 RDATA11 RFP10 RCLK10 RDATA10 RFP9 RCLK9 RDATA9 RFP8 RCLK8 RDATA8 RLCD15 RLCD14 RLCD13 RLCD12 RLCD11 RLCD10 RLCD9 RLCD8 RLCD7 RLCD6 RLCD5 RLCD4 RLCD3 RLCD2 RLCD1 RLCD0 UR_PAR UR_CLAV3 UR_CLAV2 -- UR_CLAV1 -- UR_CLAV0 -- UR_SOC UR_DATA0 UR_DATA1 UR_DATA2 TYPE observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 output3 controlr output3 controlr output3 controlr output3 output3 output3 output3 CONTROL CELL
161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 161 77 73 73 73 75 77 86 86 86
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CELL 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 NAME UR_DATA3 UR_DATA4 UR_DATA5 UR_DATA6 -- UR_DATA7 UR_CLK UR_ENB UR_ADDR0 UR_ADDR1 UR_ADDR2 UR_ADDR3 UR_ADDR4 UT_2CLAV3 UT_2CLAV2 UT_2CLAV1 UT_CLAV3 UT_CLAV2 -- UT_CLAV1 UT_2CLAV0 -- UT_CLAV0 UT_PAR UT_CLK UT_SOC UT_DATA0 UT_DATA1 UT_DATA2 UT_DATA3 UT_DATA4 UT_DATA5 UT_DATA6 UT_DATA7 UT_ENB UT_ADDR0 UT_ADDR1 UT_ADDR2 UT_ADDR3 UT_ADDR4 -- TFP7 TFP7 TCLK7 TDATA7 -- TFP6 TFP6 TCLK6 TDATA6 -- TFP5 TFP5 TCLK5 TDATA5 -- TFP4 TFP4 TCLK4 TYPE output3 output3 output3 output3 controlr output3 observe_only observe_only observe_only observe_only observe_only observe_only observe_only output3 output3 output3 output3 output3 controlr output3 output3 controlr output3 observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only CONTROL CELL 86 86 86 86 86 CELL 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 NAME TDATA4 -- TFP3 TFP3 TCLK3 TDATA3 -- TFP2 TFP2 TCLK2 TDATA2 -- TFP1 TFP1 TCLK1 TDATA1 -- TFP0 TFP0 TCLK0 -- TDATA0 RFP7 RCLK7 RDATA7 RFP6 RCLK6 RDATA6 RFP5 RCLK5 RDATA5 RFP4 RCLK4 RDATA4 RFP3 RCLK3 RDATA3 RFP2 RCLK2 RDATA2 RFP1 RCLK1 RDATA1 RFP0 RCLK0 RDATA0 INT -- INT BLS0 MUX BTS CS WR (R/W) RD (DS) D0/AD0 D0/AD0 D1/AD1 D1/AD1 TYPE output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only controlr output3 observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only output2 internal observe_only observe_only observe_only observe_only observe_only observe_only observe_only output3 observe_only output3 observe_only CONTROL CELL 161 142 161 147 161 152 161 157
100 100 100 100 100 100 103 103
161
122 161 127 161 132 161 137
187
210 210
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CELL 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 NAME D2/AD2 D2/AD2 D3/AD3 D3/AD3 D4/AD4 D4/AD4 D5/AD5 D5/AD5 D6/AD6 D6/AD6 -- D7/AD7 D7/AD7 A0 A1 A2 A3 A4 A5 A6 A7/ALE (AS) EXSTAT7 EXSTAT6 TYPE output3 observe_only output3 observe_only output3 observe_only output3 observe_only output3 observe_only controlr output3 observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only CONTROL CELL 210 210 210 210 210 210 CELL 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 NAME EXSTAT5 EXSTAT4 EXSTAT3 EXSTAT2 EXSTAT1 EXSTAT0 1SECOUT 8KHZIN GCLKIN GCLKOUT REFCLKIN RESET -- TFP15 TFP15 TCLK15 TDATA15 -- TFP14 TFP14 TCLK14 TDATA14 TYPE observe_only observe_only observe_only observe_only observe_only observe_only output3 observe_only observe_only output3 observe_only observe_only controlr output3 observe_only observe_only output3 controlr output3 observe_only observe_only output3 CONTROL CELL
161
161
235
161 240
161
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12.
OPERATING PARAMETERS
-0.3V to +5.5V -0.3V to +3.63V -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin with Respect to VSS (except VDD) Supply Voltage (VDD) Range with Respect to VSS Operating Temperature Range Storage Temperature Range Soldering Temperature
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C) PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 3.135 TYP MAX 5.5 +0.8 3.465 UNITS V V V
3.3
CAPACITANCE
(TA = +25C) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 7 7 MAX UNITS pF pF
DC CHARACTERISTICS
(VDD = 3.135V to 3.465V, TA = -40C to +85C.) PARAMETER Supply Current at 3.3V (Note 2) Input Leakage Tri-State Output Leakage Output Voltage (Io = -4.0mA) (Note 3) Output Voltage (Io = +4.0mA) (Note 3) UTOPIA VOH (Io = -8.0mA) (Note 4) UTOPIA VOL (Io = +8.0mA) (Note 4) SYMBOL IDD IIL IOL VOH VOL VOHU VOLU MIN -10.0 -10.0 2.4 2.4 0.4 TYP 85 +10.0 +10.0 0.4 MAX UNITS mA A A V V V V
Note 1: Theta-Ja is based on the package mounted on a 4-layer JEDEC board and measured in a JEDEC test chamber. Note 2: RCLK1 - n = TCLK1 - n = 2.048MHz, GCLK = 32.768MHz. Note 3: Applies to all non-UTOPIA outputs. Note 4: Applies to UTOPIA outputs.
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13.
CRITICAL TIMING INFORMATION
Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus signals.
Table 13-A. AC Characteristics--Multiplexed Parallel Port (MUX = 1)
(VDD = 3.3V 5%, TA = -40C to +85C.) (Figure 13-1, Figure 13-2, and Figure 13-3) PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times
R/W Hold Time R/W Setup Time Before DS High CS Setup Time Before DS, WR, or RD Active CS Hold Time
SYMBOL tCYC PW EL PW EH tR, tF tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PW ASH tASED tDDR tDSW
MIN 200 100 100
TYP
MAX
UNITS ns ns ns
20 10 50 20 0 10 5 15 10 20 30 10 80 50 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Read Data Hold Time Write Data Hold Time Muxed Address Valid to AS or ALE Fall Muxed Address Hold Time Delay Time DS, WR, or RD to AS or ALE Rise Pulse Width AS or ALE High Delay Time, AS or ALE to DS, WR, or RD Output Data Delay Time from DS or RD Data Setup Time
Figure 13-1. Intel Bus Read Timing (BTS = 0/MUX = 1)
t CYC ALE (A7) t ASD PW ASH t ASD RD_B PW EL CS_B t ASL AD0-AD7 t AHL t DDR t DHR t CS t ASED
WR_B
PW EH t CH
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Figure 13-2. Intel Bus Write Timing (BTS = 0/MUX = 1)
t CYC ALE (A7) RD_B WR_B PW EL CS_B t ASL AD0-AD7 t AHL t DSW t DHW t ASD t ASD PW ASH t ASED t CS
PW EH t CH
Figure 13-3. Motorola Bus Timing (BTS = 1/MUX = 1)
PWASH AS t ASD DS PWEL t RWS R/W AD0-AD7
(READ)
t ASED t CYC
PWEH
t RWH t DDR
t ASL t AHL
t DHR t CH t DSW t DHW
t CS
CS_B AD0-AD7
(WRITE)
t ASL t AHL
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Table 13-B. AC Characteristics--Nonmultiplexed Parallel Port (MUX = 1)
(VDD = 3.3V 5%, TA = -40C to +85C.) (Figure 13-4 through Figure 13-7) PARAMETER Setup Time for A[7:0], BLS0 Valid to CS Active Setup Time for CS Active to Either RD or WR Active Delay Time from Either RD or DS Active to D/AD[7:0] Valid Hold Time from Either RD or WR Inactive to CS Inactive Hold Time from CS or RD or DS Inactive to D/AD[7:0] Tri-State Wait Time from WR Active to Latch Data Data Setup Time to WR Inactive Data Hold Time from WR Inactive Address, BLS0 Hold from WR Inactive Write Access to Subsequent Write/Read Access Delay Time (Note 1) SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 0 5 30 10 2 0 5 x GCLK 25 MIN 0 0 130 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns
Note 1: Time t10 should be minimum 5 x the GCLKIN period. For a GCLKIN = 33MHz, t10 = 150ns. Note 2: Interrupt is deasserted at 5 x GCLKIN period + 40ns maximum from RD active.
Figure 13-4. Intel Bus Read Timing (BTS = 0/MUX = 0)
t9 ADDR[7:0] ADDRESS VALID
DATA[7:0]
DATA VALID
t5 WR_B t1 CS_B t2 RD_B t3 t4 t10
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Figure 13-5. Intel Bus Write Timing (BTS = 0/MUX = 0)
t9 ADDR[7:0] ADDRESS VALID
DATA[7:0] t7 RD_B t1 CS_B t2 WR_B t6 t4 t10 t8
Figure 13-6. Motorola Bus Read Timing (BTS = 1/MUX = 0)
t9 ADDR[7:0] ADDRESS VALID
DATA[7:0]
DATA VALID
t5 R/W_B t1 CS_B t2 DS_B t3 t4 t10
Figure 13-7. Motorola Bus Write Timing (BTS = 1/MUX = 0)
t9 ADDR[7:0] ADDRESS VALID
DATA[7:0] t7 R/W_B t1 CS_B t2 DS_B t6 t4 t10 t8
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Table 13-C. Framer Interface AC Characteristics
PARAMETER RCLK Duty Cycle RDATA and RFP Setup to RCLK Active Edge RDATA and RFP Hold from RCLK Active Edge TCLK Duty Cycle Output Delay TDATA and TFP from TCLK Active Edge (Note 3) TFP Setup Time to TCLK Active Edge (Note 4) TFP Hold Time from TCLK Active Edge (Note 4)
Note 3: TFP is an output. Note 4: TFP is an input.
SYMBOL
MIN 30
TYP
MAX 70
UNITS % ns ns
t11 t12
10 2 30 70 20 10 10
% ns ns ns
t13 t14 t15
Table 13-D. UTOPIA Transmit AC Characteristics
PARAMETER UT_CLK Frequency UT_CLK Duty Cycle Setup Time UT_DATA[x], UT_ADDR[x], UT_ENB, UT_SOC, UT_PAR inputs to UT_CLK Hold Time UT_DATA[x], UT_ADDR[x], UT_ENB, UT_SOC, UT_PAR Inputs from UT_CLK Output Delay UT_CLAV[x] from UT_CLK Output Tri-State Delay UT_CLAV[x] from UT_CLK t20 (ts) t21 (th) t22 (td) t23 (tz) SYMBOL MIN 0 40 10 1 20 25 TYP MAX 25 60 UNITS MHz % ns ns ns ns
Table 13-E. UTOPIA Receive AC Characteristics
PARAMETER UR_CLK Frequency UR_CLK Duty Cycle Setup Time UR_ADDR[x] and UR_ENB Inputs to UR_CLK Hold Time UR_ADDR[x] and UR_ENB Inputs from UR_CLK Output Delay UR_CLAV[x], UR_DATA[x], UR_SOC, and UR_PAR from UR_CLK Output Tri-State Delay UR_CLAV[x], UR_DATA[x], UR_SOC, and UR_PAR from UR_CLK t24 (ts) t25 (th) t26 (td) t27 (tz) SYMBOL MIN 0 40 10 1 20 25 TYP MAX 25 60 UNITS MHz % ns ns ns ns
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Figure 13-8. Setup/Hold Time Definition
CLOCK
Figure 13-9. Delay Time Definition
CLOCK SIGNAL SIGNAL
ts
INPUT SETUP TO CLOCK
th
INPUT HOLD FROM CLOCK td AND tz
Table 13-F. JTAG Interface Timing
(VDD = 3.3V 5%, TA = -40C to +85C.) (Figure 13-10) PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 5) JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO High-Z Delay
JTRST Width Low Time
Note 5: Clock can be stopped high or low.
SYMBOL t1 t2/t3 t4 t5 t6 t7 t8
MIN
TYP 1000
MAX
UNITS ns ns ns ns
50 3 2 2 2 100
500
50 50
ns ns ns
Figure 13-10. JTAG Interface Timing Diagram
t1 t2 t3
JTCLK t4 JTDI, JTMS, JTRST t6 t7 t5
JTD0
t8 JTRST
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Table 13-G. System Clock AC Characteristics
PARAMETER REFCLKIN Frequency REFCLKIN Duty Cycle GCLK Frequency GCLK Duty Cycle (Note 6) 40 16 40 SYMBOL CONDITIONS MIN TYP 1.544 2.048 60 40 60 MAX UNITS MHz % MHz %
Note 6: GCLK frequency must be at least 10 times the line rate (either 1.544MHz or 2.048MHz).
14.
THERMAL INFORMATION
Table 14-A. Thermal Properties, Natural Convection
PARAMETER Ambient Temperature Junction Temperature Theta-JA (qJA), Still Air Psi-JB Psi-JT SYMBOL CONDITIONS (Note 1) (Note 2) MIN -40C -40C TYP MAX +85C +125C UNITS
20.27C/W 8.27C/W 0.24C/W
Note 1: The package is mounted on a 4-layer JEDEC standard test board with no airflow and dissipating maximum power. Note 2: Theta-JA (qJA) is the junction to ambient thermal resistance, when the package is mounted on a 4-layer JEDEC standard test board with no airflow and dissipating maximum power.
Table 14-B. Theta-JA (qJA) vs. Airflow
FORCED AIR (m/s) 0 1 2.5 THETA-JA (qJA) 20.27C/W 17.44C/W 16.18C/W
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15.
15.1
APPLICATIONS INFORMATION
Application in ATM User-Network Interfaces
Figure 15-1 shows the application of the DS26102 in an ATM user-network interface (UNI). In a UNI, the DS26102 provides the transmission convergence sublayer functionality. The interface between the DS26102 and the ATM layer is governed by UTOPIA II specification from the ATM forum. Multiplexing with 1CLAV can be used as UTOPIA polling mode. The DS26102 supports up to 16 T1/E1 ports. For cell-rate decoupling, 4-cell buffer is allocated per port separately in the transmit and receive interfaces with the ATM layer. The buffer size of the transmit FIFO is configurable to 2, 3, or 4 cells. This flexibility in changing the FIFO depth provides users the control over cell latency, if desired.
Figure 15-1. User-Network Interface Application T1/E1 FRAMER 1 T1/E1 FRAMER 2
DS26102
ATM LAYER
T1/E1 FRAMER 16 15.2 Interfacing with Framers
Figure 15-2 shows two methods of interfacing the DS26102 to a Dallas framer. One method shows a "loop timing" method where TCLK, TSYNC/TFPx, RFPx, and RCLK are derived from the receive framer's RCLK and RSYNC. The other method shows an interface where transmit and receive are independent. The following guidelines are suggested: TCLK may be derived from RCLK. TCLK must be 1.544MHz for T1 and 2.048MHz for E1. The framer elastic stores should be disabled on both transmit and receive sides. RSYNC must be configured as a frame-boundary output. The framer TSYNC can be an input or an output (the DS26102 must be programmed accordingly). TSYNC should be configured for frame-boundary mode. The TSYNC and RSYNC signals should be high for only one TCLK and RCLK period, respectively.
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Figure 15-2. DS26102 Interfacing with Dallas Framer in Framing-Pulse Mode
DALLAS FRAMER
RCLK RSER RSYNC TCLK TSER TSYNC
DS26102
RCLKx RDATAx RFPx TCLKx TDATAx TFPx
x = 0 - 15
DALLAS FRAMER
RCLK RSER RSYNC TCLK TSER TSYNC
DS26102
RCLKx RDATAx RFPx TCLKx TDATAx TFPx
x = 0 - 15
CLOCK
When interfacing to framers where the framing pulse and data-active edge are individually configurable, ensure that the sampling and updating happen in opposite edges. Table 15-A demonstrates the recommended configurations for interfacing the DS26102 to the framer signals.
Table 15-A. Suggested Clock Edge Configurations
DATA UPDATE EDGE IN DS26102 Positive Negative Positive Negative DATA-SAMPLING EDGE IN FRAMER Negative Positive Negative Positive FRAMING-PULSE DIRECTION From DS26102 to framer From DS26102 to framer From framer to DS26102 From framer to DS26102 FRAMING-PULSE EDGE IN FRAMER Negative for sampling Positive for sampling Positive for updating Negative for updating
15.3 Fractional T1/E1 Support
Table 15-B describes the configuration needed by the DS26102 for supporting fractional T1/E1. Note that in E1 mode, the DS26102 must be used in gapped-clock mode, where the clock is gapped during inactive channels as well as TS0 and TS16 for CAS-framed format. When configured for T1, either frame-pulse or gapped-clock mode can be used, however, the TFP and RFP signals must be generated during framing overhead-bit and nonactiveDS0/TS positions of the T1 frame. Older Dallas framers may require additional logic to implement gapped-clock operation.
Table 15-B. Fractional T1/E1 Register Settings
CONTROL REGISTER BIT TPC TPLIM TFSD RPC RPLIM T1 0 0 for frame-pulse mode or 1 for gapped-clock mode 0 (input only) 0 0 for frame-pulse mode or 1 for gapped-clock mode E1 1 1 (gapped-clock mode only) 0 for TFP as input or 1 for TFP as output 1 1 (gapped-clock mode only)
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DS26102 16-Port TDM-to-ATM PHY
16.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
Note: All dimensions in millimeters.
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DS26102 16-Port TDM-to-ATM PHY
PACKAGE INFORMATION (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
Bottom Mechanical Dimensions
Note: All dimensions in millimeters.
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DS26102 16-Port TDM-to-ATM PHY
17.
REVISION HISTORY
DESCRIPTION
REVISION
021403
New product release
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